Remove MBus spad from configs that do not support it

ucb-bar · Dec 30, 2023 · ad4498b · ad4498b
1 parent 07a7f30
commit ad4498b
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Showing 7 changed files with 16 additions and 6 deletions.
diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala
@@ -30,7 +30,8 @@ class WithArtyTweaks extends Config(
   new chipyard.config.WithFrontBusFrequency(32) ++
   new chipyard.config.WithControlBusFrequency(32) ++
   new chipyard.config.WithPeripheryBusFrequency(32) ++
-  new testchipip.serdes.WithNoSerialTL
+  new testchipip.serdes.WithNoSerialTL ++
+  new testchipip.soc.WithNoScratchpads
 )
 
 class TinyRocketArtyConfig extends Config(

diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -69,10 +69,11 @@ class AbstractConfig extends Config(
       width = 32                                                    // serial-tilelink interface with 32 lanes
     )
   )) ++
+  new testchipip.soc.WithMbusScratchpad(base = 0x08000000,          // add 64 KiB on-chip scratchpad
+                                        size = 64 * 1024) ++
   new chipyard.config.WithDebugModuleAbstractDataWords(8) ++        // increase debug module data capacity
   new chipyard.config.WithBootROM ++                                // use default bootrom
   new chipyard.config.WithUART ++                                   // add a UART
-  new testchipip.soc.WithMbusScratchpad(base = 0x08000000, size = 64 * 1024) ++ // add 64 KiB on-chip scratchpad
   new chipyard.config.WithL2TLBs(1024) ++                           // use L2 TLBs
   new chipyard.config.WithNoSubsystemDrivenClocks ++                // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
   new chipyard.config.WithInheritBusFrequencyAssignments ++         // Unspecified clocks within a bus will receive the bus frequency if set

diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala
@@ -146,7 +146,7 @@ class MultiNoCConfig extends Config(
  * L2 3   | MI  | Cache[3]   |    6
  * DRAM 0 | MO  | system[0]  |    3
  * DRAM 1 | MO  | system[1]  |    5
- * extram | MO  | serial_tl_0  |    9
+ * spad   | MO  | ram[0]     |    9
  */
 // DOC include start: SharedNoCConfig
 class SharedNoCConfig extends Config(
@@ -169,7 +169,7 @@ class SharedNoCConfig extends Config(
         "Cache[0]" -> 0, "Cache[1]" -> 2, "Cache[2]" -> 8, "Cache[3]" -> 6),
       outNodeMapping = ListMap(
         "system[0]" -> 3, "system[1]" -> 5,
-        "serial_tl_0" -> 9))
+        "ram[0]" -> 9))
   )) ++
   new constellation.soc.WithSbusNoC(constellation.protocol.GlobalTLNoCParams(
     constellation.protocol.DiplomaticNetworkNodeMapping(

diff --git a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
@@ -4,6 +4,7 @@ import org.chipsalliance.cde.config.{Config}
 
 // A empty config with no cores. Useful for testing
 class NoCoresConfig extends Config(
+  new testchipip.soc.WithNoScratchpads ++
   new testchipip.boot.WithNoBootAddrReg ++
   new testchipip.boot.WithNoCustomBootPin ++
   new chipyard.config.WithNoCLINT ++

diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -12,7 +12,8 @@ class RocketConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class TinyRocketConfig extends Config(
-  new chipyard.harness.WithDontTouchChipTopPorts(false) ++         // TODO FIX: Don't dontTouch the ports
+  new chipyard.harness.WithDontTouchChipTopPorts(false) ++        // TODO FIX: Don't dontTouch the ports
+  new testchipip.soc.WithNoScratchpads ++                         // All memory is the Rokcket TCMs
   new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology
   new freechips.rocketchip.subsystem.WithNBanks(0) ++             // remove L2$
   new freechips.rocketchip.subsystem.WithNoMemPort ++             // remove backing memory

diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
@@ -7,6 +7,7 @@ import org.chipsalliance.cde.config.{Config}
 class Sodor1StageConfig extends Config(
   // Create a Sodor 1-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++
+  new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
   new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
@@ -16,6 +17,7 @@ class Sodor1StageConfig extends Config(
 class Sodor2StageConfig extends Config(
   // Create a Sodor 2-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++
+  new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
   new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
@@ -25,6 +27,7 @@ class Sodor2StageConfig extends Config(
 class Sodor3StageConfig extends Config(
   // Create a Sodor 1-stage core with two ports
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++
+  new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
   new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
@@ -34,6 +37,7 @@ class Sodor3StageConfig extends Config(
 class Sodor3StageSinglePortConfig extends Config(
   // Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter)
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++
+  new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
   new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
@@ -43,6 +47,7 @@ class Sodor3StageSinglePortConfig extends Config(
 class Sodor5StageConfig extends Config(
   // Create a Sodor 5-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++
+  new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
   new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
@@ -52,6 +57,7 @@ class Sodor5StageConfig extends Config(
 class SodorUCodeConfig extends Config(
   // Construct a Sodor microcode-based single-bus core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++
+  new testchipip.soc.WithNoScratchpads ++                      // No scratchpads
   new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory

diff --git a/generators/testchipip b/generators/testchipip