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jwright6323 committed May 4, 2020
1 parent df9567b commit 9eb4bc0
Showing 1 changed file with 3 additions and 3 deletions.
6 changes: 3 additions & 3 deletions generators/chipyard/src/main/scala/IOBinders.scala
Original file line number Diff line number Diff line change
Expand Up @@ -104,7 +104,7 @@ object AddIOCells {

/**
* Add IO cells to a SiFive UART devices and name the IO ports.
* @param gpios A Seq of UART port bundles
* @param uartPins A Seq of UART port bundles
* @return Returns a tuple of (A Seq of top-level UARTPortIO IOs; a 2D Seq of IOCell module references)
*/
def uart(uartPins: Seq[UARTPortIO]): (Seq[UARTPortIO], Seq[Seq[IOCell]]) = {
Expand All @@ -117,7 +117,7 @@ object AddIOCells {

/**
* Add IO cells to a debug module and name the IO ports.
* @param gpios A PSDIO bundle
* @param psd A PSDIO bundle
* @param resetctrlOpt An optional ResetCtrlIO bundle
* @param debugOpt An optional DebugIO bundle
* @return Returns a tuple3 of (Top-level PSDIO IO; Optional top-level DebugIO IO; a list of IOCell module references)
Expand Down Expand Up @@ -312,4 +312,4 @@ class WithTraceGenSuccessBinder extends OverrideIOBinder({
}
})

}
} /* end package object */

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