Bump rocket-chip/saturn/shuttle

* Rocket-chip now supports vector-extensions
* Fixes minor bug in shuttle load-stores
* Saturn now supports zvbb

README.md

@@ -16,7 +16,7 @@ To get started using Chipyard, see the documentation on the Chipyard documentati
 
 Chipyard is an open source framework for agile development of Chisel-based systems-on-chip.
 It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators.
-Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6 (Ariane)][cva6]), vector units ([Saturn](https://github.com/ucb-bar/saturn-vectors), [Ara](https://github.com/pulp-platform/ara)), accelerators ([Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
+Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6 (Ariane)][cva6]), vector units ([Saturn](saturn), [Ara](ara)), accelerators ([Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
 Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]).
 Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley].
 
@@ -98,3 +98,5 @@ This work is supported by the NSF CCRI ENS Chipyard Award #2016662.
 [cva6]: https://github.com/openhwgroup/cva6/
 [gemmini]: https://github.com/ucb-bar/gemmini
 [nvdla]: http://nvdla.org/
+[saturn]: https://github.com/ucb-bar/saturn-vectors
+[ara]: https://github.com/pulp-platform/ara

docs/Generators/Saturn.rst

@@ -7,13 +7,14 @@ Saturn implements a compact short-vector-length vector microarchitecture suitabl
 More documentation on Saturn will be released in the future.
 A partial listing of supported Saturn configurations is in ``generators/chipyard/src/main/scala/config/SaturnConfigs.scala``.
 
- * Full support for `V` application-profile RVV 1.0
+ * Full support for ``V`` application-profile RVV 1.0
  * Precise traps with virtual memory
  * Indexed/strided/segmented loads and stores
  * Mask operations
  * Register-gather + reductions
- * `Zvfh` support for vector half-precision floating-point (FP16)
- * `Zve64d` support for vector FP32 and FP64
- * Configurable vector length, from `Zvl64b` up (tested to `Zvl4096b`)
+ * ``Zvfh`` support for vector half-precision floating-point (FP16)
+ * ``Zvbb`` support for vector basic bit-manipulation instructions
+ * ``Zve64d`` support for vector FP32 and FP64
+ * Configurable vector length, from ``Zvl64b`` up (tested to ``Zvl4096b``)
  * Configurable datapath width, from 64b up (tested to 512b)