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Bump FireSim
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davidbiancolin authored and abejgonzalez committed Jan 17, 2022
1 parent 6b16d40 commit 8905056
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion sims/firesim
Submodule firesim updated 52 files
+1 −1 sim/build.sbt
+3 −78 sim/midas/src/main/cc/simif.cc
+22 −86 sim/midas/src/main/cc/simif.h
+3 −6 sim/midas/src/main/cc/simif_emul.cc
+2 −2 sim/midas/src/main/cc/simif_emul.h
+5 −0 sim/midas/src/main/cc/simif_f1.h
+2 −2 sim/midas/src/main/cc/unittest/Makefrag
+3 −2 sim/midas/src/main/scala/midas/passes/AutoCounterTransform.scala
+1 −1 sim/project/build.properties
+0 −23 sim/project/plugins.sbt
+18 −25 sim/src/main/cc/fasedtests/fasedtests_top.cc
+3 −3 sim/src/main/cc/fasedtests/fasedtests_top.h
+5 −1 sim/src/main/cc/fasedtests/test_harness_bridge.cc
+5 −2 sim/src/main/cc/fasedtests/test_harness_bridge.h
+3 −1 sim/src/main/cc/firesim/firesim_top.cc
+2 −2 sim/src/main/cc/midasexamples/Accumulator.h
+2 −2 sim/src/main/cc/midasexamples/AssertModule.h
+2 −2 sim/src/main/cc/midasexamples/AssertTorture.h
+2 −2 sim/src/main/cc/midasexamples/AutoCounterCoverModule.h
+4 −4 sim/src/main/cc/midasexamples/AutoCounterModule.h
+2 −2 sim/src/main/cc/midasexamples/Driver.cc
+2 −2 sim/src/main/cc/midasexamples/EnableShiftRegister.h
+2 −2 sim/src/main/cc/midasexamples/GCD.h
+2 −2 sim/src/main/cc/midasexamples/MultiReg.h
+2 −2 sim/src/main/cc/midasexamples/MultiRegfile.h
+2 −2 sim/src/main/cc/midasexamples/MultiRegfileFMR.h
+2 −2 sim/src/main/cc/midasexamples/MulticlockAssertModule.h
+1 −1 sim/src/main/cc/midasexamples/MulticlockAutoCounterModule.h
+1 −1 sim/src/main/cc/midasexamples/MulticlockPrintfModule.h
+1 −1 sim/src/main/cc/midasexamples/NarrowPrintfModule.h
+2 −2 sim/src/main/cc/midasexamples/NestedModels.h
+2 −2 sim/src/main/cc/midasexamples/Parity.h
+2 −2 sim/src/main/cc/midasexamples/PassthroughModels.h
+2 −2 sim/src/main/cc/midasexamples/PointerChaser.h
+6 −6 sim/src/main/cc/midasexamples/PrintfModule.h
+2 −2 sim/src/main/cc/midasexamples/Regfile.h
+2 −2 sim/src/main/cc/midasexamples/ResetPulseBridgeTest.h
+2 −2 sim/src/main/cc/midasexamples/ResetShiftRegister.h
+2 −2 sim/src/main/cc/midasexamples/Risc.h
+2 −2 sim/src/main/cc/midasexamples/ShiftRegister.h
+2 −2 sim/src/main/cc/midasexamples/Stack.h
+2 −2 sim/src/main/cc/midasexamples/TriggerWiringModule.h
+4 −4 sim/src/main/cc/midasexamples/TrivialMulticlock.h
+2 −2 sim/src/main/cc/midasexamples/TwoAdders.h
+2 −2 sim/src/main/cc/midasexamples/VerilogAccumulator.h
+2 −2 sim/src/main/cc/midasexamples/WireInterconnect.h
+131 −0 sim/src/main/cc/midasexamples/simif_peek_poke.cc
+77 −0 sim/src/main/cc/midasexamples/simif_peek_poke.h
+5 −4 sim/src/main/makefrag/fasedtests/Makefrag
+6 −4 sim/src/main/makefrag/midasexamples/Makefrag
+7 −3 sim/src/main/scala/fasedtests/AXI4Fuzzer.scala
+1 −1 target-design/chipyard

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