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Merge pull request #976 from ucb-bar/bump-firesim
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Bump Firesim + Use ResetPulseBridge
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davidbiancolin authored Sep 13, 2021
2 parents 4386552 + 580d311 commit 64aa972
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Showing 3 changed files with 27 additions and 6 deletions.
13 changes: 10 additions & 3 deletions .circleci/run-firesim-scala-tests.sh
Original file line number Diff line number Diff line change
Expand Up @@ -13,13 +13,20 @@ source $SCRIPT_DIR/defaults.sh
# call clean on exit
trap clean EXIT

# Directory locations for handling firesim-local installations of libelf/libdwarf
# This would generally be handled by build-setup.sh/firesim-setup.sh
firesim_sysroot=lib-install
local_firesim_sysroot=$LOCAL_FIRESIM_DIR/$firesim_sysroot
remote_firesim_sysroot=$REMOTE_FIRESIM_DIR/$firesim_sysroot

cd $LOCAL_CHIPYARD_DIR
./scripts/init-submodules-no-riscv-tools.sh
cd $LOCAL_CHIPYARD_DIR/sims/firesim/sim/firesim-lib/src/main/cc/lib
git submodule update --init elfutils libdwarf
cd $LOCAL_CHIPYARD_DIR/sims/firesim
./scripts/build-libelf.sh
./scripts/build-libdwarf.sh
mkdir -p $local_firesim_sysroot
./scripts/build-libelf.sh $local_firesim_sysroot
./scripts/build-libdwarf.sh $local_firesim_sysroot
cd $LOCAL_CHIPYARD_DIR

# replace the workspace dir with a local dir so you can copy around
Expand All @@ -42,8 +49,8 @@ run "cp -r ~/.ivy2 $REMOTE_WORK_DIR"
run "cp -r ~/.sbt $REMOTE_WORK_DIR"

TOOLS_DIR=$REMOTE_RISCV_DIR
LD_LIB_DIR=$REMOTE_RISCV_DIR/lib

LD_LIB_DIR=$remote_firesim_sysroot/lib:$REMOTE_RISCV_DIR/lib

# Run Firesim Scala Tests
run "export RISCV=\"$TOOLS_DIR\"; \
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18 changes: 16 additions & 2 deletions generators/firechip/src/main/scala/FireSim.scala
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ import freechips.rocketchip.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, InModuleBody, ValName}
import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap}

import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock}
import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock, ResetPulseBridge, ResetPulseBridgeParameters}

import chipyard._
import chipyard.harness._
Expand Down Expand Up @@ -227,7 +227,21 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessSigna

val buildtopClock = Wire(Clock())
val buildtopReset = WireInit(false.B)
val peekPokeBridge = PeekPokeBridge(buildtopClock, buildtopReset)
// The peek-poke bridge must still be instantiated even though it's
// functionally unused. This will be removed in a future PR.
val dummy = WireInit(false.B)
val peekPokeBridge = PeekPokeBridge(buildtopClock, dummy)

val resetBridge = Module(new ResetPulseBridge(ResetPulseBridgeParameters()))
// In effect, the bridge counts the length of the reset in terms of this clock.
resetBridge.io.clock := buildtopClock
buildtopReset := resetBridge.io.reset
// Ensures FireSim-synthesized assertions and instrumentation is disabled
// while buildtopReset is asserted. This ensures assertions do not fire at
// time zero in the event their local reset is delayed (typically because it
// has been pipelined)
midas.targetutils.GlobalResetCondition(buildtopReset)

def dutReset = { require(false, "dutReset should not be used in Firesim"); false.B }
def success = { require(false, "success should not be used in Firesim"); false.B }

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2 changes: 1 addition & 1 deletion sims/firesim
Submodule firesim updated 114 files

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