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Bump FireSim
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@davidbiancolin
davidbiancolin committed Dec 2, 2021
1 parent 0a513e4 commit 5886a84
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion sims/firesim
Submodule firesim updated 60 files
+5 −22 .circleci/common.py
+7 −1 .circleci/cull-old-ci-instances.py
+7 −26 .circleci/launch-manager-instance.py
+1 −0 .circleci/requirements.txt
+11 −1 build-setup-nolog.sh
+83 −24 deploy/awstools/awstools.py
+0 −10 deploy/firesim
+26 −0 deploy/regression.sh
+22 −2 deploy/runtools/firesim_topology_elements.py
+1 −1 deploy/sample-backup-configs/sample_config_build_recipes.ini
+1 −1 deploy/sample-backup-configs/sample_config_runtime.ini
+32 −3 docs/Advanced-Usage/FAQs.rst
+1 −1 docs/Advanced-Usage/Manager/Manager-Tasks.rst
+4 −3 docs/Advanced-Usage/Workloads/Defining-Custom-Workloads.rst
+1 −1 docs/Golden-Gate/Output-Files.rst
+1 −1 docs/Initial-Setup/Setting-up-your-Manager-Instance.rst
+1 −1 platforms/f1/aws-fpga
+7 −2 scripts/machine-launch-script.sh
+5 −2 sim/Makefile
+9 −20 sim/build.sbt
+2 −2 sim/midas/src/main/cc/Makefile
+2 −2 sim/midas/src/main/cc/simif.cc
+2 −4 sim/midas/src/main/cc/simif_emul.cc
+0 −4 sim/midas/src/main/cc/simif_f1.cc
+0 −33 sim/midas/src/main/cc/simif_zynq.cc
+0 −27 sim/midas/src/main/cc/simif_zynq.h
+0 −4 sim/midas/src/main/cc/utils/utils.mk
+0 −21 sim/midas/src/main/scala/midas/Config.scala
+0 −1 sim/midas/src/main/scala/midas/FPGAQoRShimGenerator.scala
+0 −1 sim/midas/src/main/scala/midas/SynthUnitTests.scala
+1 −1 sim/midas/src/main/scala/midas/models/dram/FASEDMemoryTimingModel.scala
+3 −3 sim/midas/src/main/scala/midas/passes/AutoCounterTransform.scala
+0 −23 sim/midas/src/main/scala/midas/platform/ZynqShim.scala
+46 −0 sim/midas/src/main/scala/midas/stage/AddDerivedAnnotations.scala
+1 −3 sim/midas/src/main/scala/midas/stage/Annotations.scala
+70 −0 sim/midas/src/main/scala/midas/stage/Checks.scala
+1 −3 sim/midas/src/main/scala/midas/stage/GoldenGateCli.scala
+4 −2 sim/midas/src/main/scala/midas/stage/GoldenGateCompilerPhase.scala
+3 −4 sim/midas/src/main/scala/midas/stage/GoldenGateStage.scala
+5 −4 sim/midas/src/main/scala/midas/stage/RuntimeConfigGenerationPhase.scala
+1 −0 sim/midas/src/main/scala/midas/stage/RuntimeConfigGeneratorStage.scala
+3 −1 sim/midas/src/main/scala/midas/stage/phases/CreateParametersInstancePhase.scala
+57 −35 sim/midas/src/main/scala/midas/widgets/Lib.scala
+1 −1 sim/midas/src/main/scala/midas/widgets/PeekPokeIO.scala
+10 −11 sim/midas/src/main/scala/midas/widgets/Widget.scala
+1 −1 sim/midas/src/main/verilog/BUFGCE.v
+4 −4 sim/midas/src/main/verilog/vcs_top.v
+476 −0 sim/midas/src/test/scala/firrtl/testutils/FirrtlSpec.scala
+55 −0 sim/midas/src/test/scala/firrtl/testutils/LeanTransformSpec.scala
+108 −0 sim/midas/src/test/scala/firrtl/testutils/PassTests.scala
+36 −0 sim/midas/src/test/scala/midas/stage/AddDerivedAnnotationsSpec.scala
+54 −0 sim/midas/src/test/scala/midas/stage/ChecksSpec.scala
+10 −2 sim/midas/targetutils/src/main/scala/midas/annotations.scala
+43 −0 sim/midas/targetutils/src/test/scala/ElaborationUtils.scala
+16 −0 sim/midas/targetutils/src/test/scala/FpgaDebugSpec.scala
+16 −0 sim/midas/targetutils/src/test/scala/PerfCounterSpec.scala
+0 −2 sim/src/main/scala/fasedtests/Config.scala
+4 −4 sim/src/main/scala/midasexamples/AutoCounterModule.scala
+0 −2 sim/src/test/scala/fasedtests/FASEDTestSuite.scala
+2 −2 sim/target-agnostic.mk

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