Merge pull request #766 from ucb-bar/doc-update

Docs and README update
ucb-bar · Jan 19, 2021 · 55e4a1a · 55e4a1a
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diff --git a/README.md b/README.md
@@ -47,12 +47,16 @@ If used for research, please cite Chipyard by the following publication:
 }
 ```
 
+* **Chipyard**
+    * A. Amid, et al. *IEEE Micro'20* [PDF](https://ieeexplore.ieee.org/document/9099108).
+    * A. Amid, et al. *DAC'20* [PDF](https://ieeexplore.ieee.org/document/9218756).
+
 These additional publications cover many of the internal components used in Chipyard. However, for the most up-to-date details, users should refer to the Chipyard docs.
 
 * **Generators**
     * **Rocket Chip**: K. Asanovic, et al., *UCB EECS TR*. [PDF](http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.pdf).
     * **BOOM**: C. Celio, et al., *Hot Chips 30*. [PDF](https://www.hotchips.org/hc30/1conf/1.03_Berkeley_BROOM_HC30.Berkeley.Celio.v02.pdf).
-      * **SonicBOOM (BOOMv3): J. Zhao, et al., *CARRV'20*. [PDF](https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf).
+      * **SonicBOOM (BOOMv3)**: J. Zhao, et al., *CARRV'20*. [PDF](https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf).
     * **Hwacha**: Y. Lee, et al., *ESSCIRC'14*. [PDF](http://hwacha.org/papers/riscv-esscirc2014.pdf).
     * **Gemmini**: H. Genc, et al., *arXiv*. [PDF](https://arxiv.org/pdf/1911.09925).
 * **Sims**

diff --git a/docs/TileLink-Diplomacy-Reference/Widgets.rst b/docs/TileLink-Diplomacy-Reference/Widgets.rst
@@ -200,10 +200,11 @@ transactions.
 AXI4Fragmenter
 --------------
 
-The AXI4Fragmenter is similar to the :ref:`TileLink-Diplomacy-Reference/Widgets:TLFragmenter`, except it can only
-break multi-beat AXI4 transactions into single-beat transactions. This
-effectively serves as an AXI4 to AXI4-Lite converter. The constructor for this
-widget does not take any arguments.
+The AXI4Fragmenter is similar to the :ref:`TileLink-Diplomacy-Reference/Widgets:TLFragmenter`.
+The AXI4Fragmenter slices all AXI accesses into simple power-of-two sized and aligned transfers
+of the largest size supported by the manager. This makes it suitable as a first stage transformation
+to apply before an AXI4=>TL bridge. It also makes it suitable for placing after TL=>AXI4 bridge
+driving an AXI-lite slave.
 
 **Example Usage:**