Rename SerialAdapter+SimSerial to TSIToTileLink/SimTSI/TSIHarness

docs/Advanced-Concepts/Chip-Communication.rst

@@ -47,12 +47,12 @@ Using the Tethered Serial Interface (TSI)
 By default, Chipyard uses the Tethered Serial Interface (TSI) to communicate with the DUT.
 TSI protocol is an implementation of HTIF that is used to send commands to the RISC-V DUT.
 These TSI commands are simple R/W commands that are able to access the DUT's memory space.
-During simulation, the host sends TSI commands to a simulation stub in the test harness called ``SimSerial``
-(C++ class) that resides in a ``SimSerial`` Verilog module (both are located in the ``generators/testchipip``
+During simulation, the host sends TSI commands to a simulation stub in the test harness called ``SimTSI``
+(C++ class) that resides in a ``SimTSI`` Verilog module (both are located in the ``generators/testchipip``
 project).
-This ``SimSerial`` Verilog module then sends the TSI command recieved by the simulation stub
+This ``SimTSI`` Verilog module then sends the TSI command recieved by the simulation stub
 to an adapter that converts the TSI command into a TileLink request.
-This conversion is done by the ``SerialAdapter`` module (located in the ``generators/testchipip`` project).
+This conversion is done by the ``TSIToTileLink`` module (located in the ``generators/testchipip`` project).
 After the transaction is converted to TileLink, the ``TLSerdesser`` (located in ``generators/testchipip``) serializes the
 transaction and sends it to the chip (this ``TLSerdesser`` is sometimes also referred to as a digital serial-link or SerDes).
 Once the serialized transaction is received on the chip, it is deserialized and masters a TileLink bus on the chip
@@ -76,7 +76,7 @@ simulation stub called ``SimDTM`` (C++ class) that resides in a ``SimDTM`` Veril
 sends the DMI command recieved by the simulation stub into the DUT which then converts the DMI
 command into a TileLink request. This conversion is done by the DTM named ``DebugModule`` in the ``generators/rocket-chip`` project.
 When the DTM receives the program to load, it starts to write the binary byte-wise into memory.
-This is considerably slower than the TSI protocol communication pipeline (i.e. ``SimSerial``/``SerialAdapter``/TileLink)
+This is considerably slower than the TSI protocol communication pipeline (i.e. ``SimTSI``/``TSIToTileLink``/TileLink)
 which directly writes the program binary to memory.
 
 Starting the TSI or DMI Simulation
@@ -216,7 +216,7 @@ Softcore-driven Bringup Setup of the Example Test Chip after Tapeout
 Assuming this example test chip is taped out and now ready to be tested, we can communicate with the chip using this serial-link.
 For example, a common test setup used at Berkeley to evaluate Chipyard-based test-chips includes an FPGA running a RISC-V soft-core that is able to speak to the DUT (over an FMC).
 This RISC-V soft-core would serve as the host of the test that will run on the DUT.
-This is done by the RISC-V soft-core running FESVR, sending TSI commands to a ``SerialAdapter`` / ``TLSerdesser`` programmed on the FPGA.
+This is done by the RISC-V soft-core running FESVR, sending TSI commands to a ``TSIToTileLink`` / ``TLSerdesser`` programmed on the FPGA.
 Once the commands are converted to serialized TileLink, then they can be sent over some medium to the DUT
 (like an FMC cable or a set of wires connecting FPGA outputs to the DUT board).
 Similar to simulation, if the chip requests offchip memory, it can then send the transaction back over the serial-link.

docs/Advanced-Concepts/Resources.rst

@@ -2,24 +2,24 @@ Accessing Scala Resources
 ===============================
 
 A simple way to copy over a source file to the build directory to be used for a simulation compile or VLSI flow is to use the ``addResource`` function given by FIRRTL.
-An example of its use can be seen in `generators/testchipip/src/main/scala/SerialAdapter.scala <https://github.com/ucb-bar/testchipip/blob/master/src/main/scala/SerialAdapter.scala>`_.
+An example of its use can be seen in `generators/testchipip/src/main/scala/SimTSI.scala <https://github.com/ucb-bar/testchipip/blob/master/src/main/scala/SimTSI.scala>`_.
 Here is the example inlined:
 
 .. code-block:: scala
 
-    class SimSerial(w: Int) extends BlackBox with HasBlackBoxResource {
+    class SimTSI extends BlackBox with HasBlackBoxResource {
       val io = IO(new Bundle {
         val clock = Input(Clock())
         val reset = Input(Bool())
-        val serial = Flipped(new SerialIO(w))
+        val tsi = Flipped(new TSIIO)
         val exit = Output(Bool())
       })
 
-      addResource("/testchipip/vsrc/SimSerial.v")
-      addResource("/testchipip/csrc/SimSerial.cc")
+      addResource("/testchipip/vsrc/SimTSI.v")
+      addResource("/testchipip/csrc/SimTSI.cc")
     }
 
-In this example, the ``SimSerial`` files will be copied from a specific folder (in this case the ``path/to/testchipip/src/main/resources/testchipip/...``) to the build folder.
+In this example, the ``SimTSI`` files will be copied from a specific folder (in this case the ``path/to/testchipip/src/main/resources/testchipip/...``) to the build folder.
 The ``addResource`` path retrieves resources from the ``src/main/resources`` directory.
 So to get an item at ``src/main/resources/fileA.v`` you can use ``addResource("/fileA.v")``.
 However, one caveat of this approach is that to retrieve the file during the FIRRTL compile, you must have that project in the FIRRTL compiler's classpath.

docs/Chipyard-Basics/Configs-Parameters-Mixins.rst

@@ -83,8 +83,8 @@ This example shows the Chipyard default top that composes multiple traits togeth
     :end-before: DOC include end: DigitalTop
 
 
-There are two "cakes" or mixins here. One for the lazy module (ex. ``CanHavePeripherySerial``) and one for the lazy module
-implementation (ex. ``CanHavePeripherySerialModuleImp`` where ``Imp`` refers to implementation). The lazy module defines
+There are two "cakes" or mixins here. One for the lazy module (ex. ``CanHavePeripheryTLSerial``) and one for the lazy module
+implementation (ex. ``CanHavePeripheryTLSerialModuleImp`` where ``Imp`` refers to implementation). The lazy module defines
 all the logical connections between generators and exchanges configuration information among them, while the
 lazy module implementation performs the actual Chisel RTL elaboration.
 
@@ -93,19 +93,17 @@ In the ``DigitalTop`` example class, the "outer" ``DigitalTop`` instantiates the
 of the module until all logical connections are determined and all configuration information is exchanged.
 The ``System`` outer base class, as well as the
 ``CanHavePeriphery<X>`` outer traits contain code to perform high-level logical
-connections. For example, the ``CanHavePeripherySerial`` outer trait contains code
-to optionally lazily instantiate the ``SerialAdapter``, and connect the ``SerialAdapter``'s
+connections. For example, the ``CanHavePeripheryTLSerial`` outer trait contains code
+to optionally lazily instantiate the ``TLSerdesser``, and connect the ``TLSerdesser`` 's
 TileLink node to the Front bus.
 
 The ``ModuleImp`` classes and traits perform elaboration of real RTL.
-For example, the ``CanHavePeripherySerialModuleImp`` trait optionally physically connects
-the ``SerialAdapter`` module, and instantiates queues.
 
 In the test harness, the SoC is elaborated with
 ``val dut = p(BuildTop)(p)``.
 
 After elaboration, the system submodule of ``ChipTop`` will be a ``DigitalTop`` module, which contains a
-``SerialAdapter`` module (among others), if the config specified for that block to be instantiated.
+``TLSerdesser`` module (among others), if the config specified for that block to be instantiated.
 
 From a high level, classes which extend ``LazyModule`` *must* reference
 their module implementation through ``lazy val module``, and they
@@ -116,7 +114,7 @@ other normal modules OR lazy modules (for nested Diplomacy
 graphs, for example).
 
 The naming convention for an additive mixin or trait is ``CanHave<YourMixin>``.
-This is shown in the ``Top`` class where things such as ``CanHavePeripherySerial`` connect a RTL component to a bus and expose signals to the top-level.
+This is shown in the ``Top`` class where things such as ``CanHavePeripheryTLSerial`` connect a RTL component to a bus and expose signals to the top-level.
 
 Additional References
 ---------------------------

docs/Generators/TestChipIP.rst

@@ -2,16 +2,16 @@ Test Chip IP
 ============
 
 Chipyard includes a Test Chip IP library which provides various hardware
-widgets that may be useful when designing SoCs. This includes a :ref:`Generators/TestChipIP:Serial Adapter`,
+widgets that may be useful when designing SoCs. This includes a :ref:`Generators/TestChipIP:SimTSI`,
 :ref:`Generators/TestChipIP:Block Device Controller`, :ref:`Generators/TestChipIP:TileLink SERDES`, :ref:`Generators/TestChipIP:TileLink Switcher`,
 :ref:`Generators/TestChipIP:TileLink Ring Network`, and :ref:`Generators/TestChipIP:UART Adapter`.
 
-Serial Adapter
+SimTSI
 --------------
 
-The serial adapter is used by tethered test chips to communicate with the host
+The SimTSI and TSIToTileLink are used by tethered test chips to communicate with the host
 processor. An instance of RISC-V frontend server running on the host CPU
-can send commands to the serial adapter to read and write data from the memory
+can send commands to the TSIToTileLink to read and write data from the memory
 system. The frontend server uses this functionality to load the test program
 into memory and to poll for completion of the program. More information on
 this can be found in :ref:`Customization/Boot-Process:Chipyard Boot Process`.

fpga/src/main/scala/arty100t/HarnessBinders.scala

@@ -28,22 +28,22 @@ class WithArty100TUARTTSI(uartBaudRate: BigInt = 115200) extends OverrideHarness
       val bits = port.bits
       port.clock := th.buildtopClock
       withClockAndReset(th.buildtopClock, th.buildtopReset) {
-        val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset)
+        val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.buildtopReset)
         val uart_to_serial = Module(new UARTToSerial(
           freq, UARTParams(0, initBaudRate=uartBaudRate)))
         val serial_width_adapter = Module(new SerialWidthAdapter(
-          narrowW = 8, wideW = SerialAdapter.SERIAL_TSI_WIDTH))
+          narrowW = 8, wideW = TSI.WIDTH))
         serial_width_adapter.io.narrow.flipConnect(uart_to_serial.io.serial)
 
-        ram.module.io.tsi_ser.flipConnect(serial_width_adapter.io.wide)
+        ram.module.io.tsi.flipConnect(serial_width_adapter.io.wide)
 
         ath.io_uart_bb.bundle <> uart_to_serial.io.uart
         ath.other_leds(1) := uart_to_serial.io.dropped
 
-        ath.other_leds(9) := ram.module.io.adapter_state(0)
-        ath.other_leds(10) := ram.module.io.adapter_state(1)
-        ath.other_leds(11) := ram.module.io.adapter_state(2)
-        ath.other_leds(12) := ram.module.io.adapter_state(3)
+        ath.other_leds(9) := ram.module.io.tsi2tl_state(0)
+        ath.other_leds(10) := ram.module.io.tsi2tl_state(1)
+        ath.other_leds(11) := ram.module.io.tsi2tl_state(2)
+        ath.other_leds(12) := ram.module.io.tsi2tl_state(3)
       }
     })
   }

generators/chipyard/src/main/scala/HarnessBinders.scala

@@ -157,13 +157,13 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
           val memOverSerialTLClockBundle = th.harnessClockInstantiator.requestClockBundle("mem_over_serial_tl_clock", memFreq)
           val serial_bits = port.bits
           port.clock := th.buildtopClock
-          val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM(
+          val harnessMultiClockAXIRAM = TSIHarness.connectMultiClockAXIRAM(
             system.serdesser.get,
             serial_bits,
             memOverSerialTLClockBundle,
             th.buildtopReset)
 // DOC include end: HarnessClockInstantiatorEx
-          val success = SerialAdapter.connectSimSerial(harnessMultiClockAXIRAM.module.io.tsi_ser, th.buildtopClock, th.buildtopReset.asBool)
+          val success = SimTSI.connect(Some(harnessMultiClockAXIRAM.module.io.tsi), th.buildtopClock, th.buildtopReset.asBool)
           when (success) { th.success := true.B }
 
           // connect SimDRAM from the AXI port coming from the harness multi clock axi ram
@@ -299,7 +299,7 @@ class WithTiedOffDebug extends OverrideHarnessBinder({
 })
 
 
-class WithSerialAdapterTiedOff extends OverrideHarnessBinder({
+class WithSerialTLTiedOff extends OverrideHarnessBinder({
   (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
     implicit val p = chipyard.iobinders.GetSystemParameters(system)
     ports.map({ port =>
@@ -312,15 +312,15 @@ class WithSerialAdapterTiedOff extends OverrideHarnessBinder({
   }
 })
 
-class WithSimSerial extends OverrideHarnessBinder({
+class WithSimTSIOverSerialTL extends OverrideHarnessBinder({
   (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
     implicit val p = chipyard.iobinders.GetSystemParameters(system)
     ports.map({ port =>
       val bits = port.bits
       port.clock := th.buildtopClock
       withClockAndReset(th.buildtopClock, th.buildtopReset) {
-        val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset)
-        val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, th.buildtopClock, th.buildtopReset.asBool)
+        val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.buildtopReset)
+        val success = SimTSI.connect(Some(ram.module.io.tsi), th.buildtopClock, th.buildtopReset.asBool)
         when (success) { th.success := true.B }
       }
     })
@@ -335,11 +335,11 @@ class WithUARTSerial extends OverrideHarnessBinder({
       val bits = port.bits
       port.clock := th.buildtopClock
       withClockAndReset(th.buildtopClock, th.buildtopReset) {
-        val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset)
+        val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.buildtopReset)
         val uart_to_serial = Module(new UARTToSerial(freq, UARTParams(0)))
         val serial_width_adapter = Module(new SerialWidthAdapter(
-          8, SerialAdapter.SERIAL_TSI_WIDTH))
-        ram.module.io.tsi_ser.flipConnect(serial_width_adapter.io.wide)
+          8, TSI.WIDTH))
+        ram.module.io.tsi.flipConnect(serial_width_adapter.io.wide)
         UARTAdapter.connect(Seq(uart_to_serial.io.uart), uart_to_serial.div)
         serial_width_adapter.io.narrow.flipConnect(uart_to_serial.io.serial)
         th.success := false.B

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -14,7 +14,7 @@ class AbstractConfig extends Config(
   // The HarnessBinders control generation of hardware in the TestHarness
   new chipyard.harness.WithUARTAdapter ++                       // add UART adapter to display UART on stdout, if uart is present
   new chipyard.harness.WithBlackBoxSimMem ++                    // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled
-  new chipyard.harness.WithSimSerial ++                         // add external serial-adapter and RAM
+  new chipyard.harness.WithSimTSIOverSerialTL ++                // add external serial-adapter and RAM
   new chipyard.harness.WithSimDebug ++                          // add SimJTAG or SimDTM adapters if debug module is enabled
   new chipyard.harness.WithGPIOTiedOff ++                       // tie-off chiptop GPIOs, if GPIOs are present
   new chipyard.harness.WithSimSPIFlashModel ++                  // add simulated SPI flash memory, if SPI is enabled

generators/chipyard/src/main/scala/config/BoomConfigs.scala

@@ -55,15 +55,15 @@ class MediumBoomCosimConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class dmiMediumBoomConfig extends Config(
-  new chipyard.harness.WithSerialAdapterTiedOff ++               // don't attach an external SimSerial
+  new chipyard.harness.WithSerialTLTiedOff ++                    // don't attach anything to serial-tl
   new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
   new boom.common.WithNMediumBooms(1) ++
   new chipyard.config.AbstractConfig)
 
 class dmiMediumBoomCosimConfig extends Config(
   new chipyard.harness.WithCospike ++                            // attach spike-cosim
   new chipyard.config.WithTraceIO ++                             // enable the traceio
-  new chipyard.harness.WithSerialAdapterTiedOff ++               // don't attach an external SimSerial
+  new chipyard.harness.WithSerialTLTiedOff ++                    // don't attach anythint to serial-tl
   new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
   new boom.common.WithNMediumBooms(1) ++
   new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/CVA6Configs.scala

@@ -13,7 +13,7 @@ class CVA6Config extends Config(
   new chipyard.config.AbstractConfig)
 
 class dmiCVA6Config extends Config(
-  new chipyard.harness.WithSerialAdapterTiedOff ++ // Tie off the serial port, override default instantiation of SimSerial
+  new chipyard.harness.WithSerialTLTiedOff ++      // Tie off the serial-tilelink port
   new chipyard.config.WithDMIDTM ++                // have debug module expose a clocked DMI port
   new cva6.WithNCVA6Cores(1) ++                    // single CVA6 core
   new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala

@@ -58,7 +58,7 @@ class LBWIFRocketConfig extends Config(
 
 // DOC include start: DmiRocket
 class dmiRocketConfig extends Config(
-  new chipyard.harness.WithSerialAdapterTiedOff ++               // don't attach an external SimSerial
+  new chipyard.harness.WithSerialTLTiedOff ++                    // don't attach anything to serial-tl
   new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/SpikeConfigs.scala

@@ -11,7 +11,7 @@ class SpikeConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class dmiSpikeConfig extends Config(
-  new chipyard.harness.WithSerialAdapterTiedOff ++               // don't attach an external SimSerial
+  new chipyard.harness.WithSerialTLTiedOff ++                    // don't attach anything to serial-tilelink
   new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
   new SpikeConfig)
 
@@ -35,7 +35,7 @@ class SpikeUltraFastConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class dmiSpikeUltraFastConfig extends Config(
-  new chipyard.harness.WithSerialAdapterTiedOff ++               // don't attach an external SimSerial
+  new chipyard.harness.WithSerialTLTiedOff ++                    // don't attach anything to serial-tilelink
   new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
   new SpikeUltraFastConfig)
 

generators/chipyard/src/main/scala/example/FlatTestHarness.scala

@@ -11,7 +11,7 @@ import freechips.rocketchip.util.{PlusArg}
 import freechips.rocketchip.subsystem.{CacheBlockBytes}
 import freechips.rocketchip.devices.debug.{SimJTAG}
 import freechips.rocketchip.jtag.{JTAGIO}
-import testchipip.{SerialTLKey, SerialAdapter, UARTAdapter, SimDRAM}
+import testchipip.{SerialTLKey, UARTAdapter, SimDRAM, TSIHarness, SimTSI}
 import chipyard.{BuildTop}
 
 // A "flat" TestHarness that doesn't use IOBinders
@@ -51,12 +51,12 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
     memOverSerialTLClockBundle.reset := reset
     val serial_bits = dut.serial_tl_pad.bits
     dut.serial_tl_pad.clock := clock
-    val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM(
+    val harnessMultiClockAXIRAM = TSIHarness.connectMultiClockAXIRAM(
       lazyDut.system.serdesser.get,
       serial_bits,
       memOverSerialTLClockBundle,
       reset)
-    io.success := SerialAdapter.connectSimSerial(harnessMultiClockAXIRAM.module.io.tsi_ser, clock, reset)
+    io.success := SimTSI.connect(Some(harnessMultiClockAXIRAM.module.io.tsi), clock, reset)
 
     // connect SimDRAM from the AXI port coming from the harness multi clock axi ram
     (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) =>