Merge pull request #1894 from ucb-bar/naming

Bump rc/components to improve module naming
ucb-bar · Jun 27, 2024 · 3174314 · 3174314
2 parents e7fc86c + 2bd10de
commit 3174314
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Showing 13 changed files with 17 additions and 17 deletions.
diff --git a/build.sbt b/build.sbt
@@ -98,8 +98,8 @@ lazy val chisel6Settings = Seq(
   addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % "6.0.0" cross CrossVersion.full)
 )
 lazy val chisel3Settings = Seq(
-  libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % "3.6.0"),
-  addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.6.0" cross CrossVersion.full)
+  libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % "3.6.1"),
+  addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.6.1" cross CrossVersion.full)
 )
 
 lazy val chiselSettings = (if (chisel6) chisel6Settings else chisel3Settings) ++ Seq(

diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
@@ -27,9 +27,9 @@ class WithPLLSelectorDividerClockGenerator(enable: Boolean = true) extends Overr
     val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes, enable=enable)) }
     val pllCtrl       = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl    (baseAddress + 0x40000, tlbus.beatBytes)) }
 
-    clockDivider.tlNode  := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
-    clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
-    pllCtrl.tlNode       := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
+    clockDivider.tlNode  := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockDivider")) := system.prci_ctrl_bus.get }
+    clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockSelector")) := system.prci_ctrl_bus.get }
+    pllCtrl.tlNode       := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("PLLCtrl")) := system.prci_ctrl_bus.get }
 
     system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
 

diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala
@@ -28,6 +28,7 @@ class ClockGroupParameterModifier(
     sinkFn:   ClockGroupSinkParameters   => ClockGroupSinkParameters   = { s => s })(
     implicit p: Parameters, v: ValName) extends LazyModule {
   val node = ClockGroupAdapterNode(sourceFn, sinkFn)
+  override def shouldBeInlined = true
   lazy val module = new LazyRawModuleImp(this) {
     (node.out zip node.in).map { case ((o, _), (i, _)) =>
       (o.member.data zip i.member.data).foreach { case (oD, iD) => oD := iD }

diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
@@ -40,7 +40,7 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement
   val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl")
     .suggestName("chipyard_prcictrl_domain")
 
-  val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } }
+  val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar(nameSuffix = Some("prcibus")) } }
   prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar
     := TLFIFOFixer(TLFIFOFixer.all)
     := TLBuffer()
@@ -71,13 +71,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement
   }
   val tileClockGater     = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain {
     val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes))
-    clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get
+    clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileClockGater")) := prci_ctrl_bus.get
     clock_gater
   } }
   val tileResetSetter    = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain {
     val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes,
       tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil))
-    reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get
+    reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileResetSetter")) := prci_ctrl_bus.get
     reset_setter
   } }
 

diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -123,7 +123,6 @@ class AbstractConfig extends Config(
   new freechips.rocketchip.subsystem.WithCoherentBusTopology ++     /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */
   new chipyard.config.WithSV48IfPossible ++                         /** use sv48 if possible */
 
-
   // ================================================
   //   Set up power, reset and clocking
   // ================================================

diff --git a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
@@ -13,9 +13,9 @@ class NoCoresConfig extends Config(
   new chipyard.config.WithNoUART ++
   new chipyard.config.WithNoTileClockGaters ++
   new chipyard.config.WithNoTileResetSetters ++
-  new chipyard.config.WithNoBusErrorDevices ++
   new chipyard.config.WithNoDebug ++
   new chipyard.config.WithNoPLIC ++
+  new chipyard.config.WithNoBusErrorDevices ++
   new chipyard.config.AbstractConfig)
 
 // A config that uses a empty chiptop module with no rocket-chip soc components

diff --git a/generators/diplomacy b/generators/diplomacy
diff --git a/generators/hardfloat b/generators/hardfloat
diff --git a/generators/rocket-chip b/generators/rocket-chip
diff --git a/generators/rocket-chip-blocks b/generators/rocket-chip-blocks
diff --git a/generators/rocket-chip-inclusive-cache b/generators/rocket-chip-inclusive-cache
diff --git a/generators/testchipip b/generators/testchipip
diff --git a/sims/firesim b/sims/firesim