Support variable MMU capabilities in cosim

ucb-bar · Aug 6, 2024 · 2e6a1ff · 2e6a1ff
1 parent d0a9520
commit 2e6a1ff
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diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
@@ -487,6 +487,7 @@ class WithTraceIOPunchthrough extends OverrideLazyIOBinder({
       val cfg = SpikeCosimConfig(
         isa = tiles.headOption.map(_.isaDTS).getOrElse(""),
         priv = tiles.headOption.map(t => if (t.usingUser) "MSU" else if (t.usingSupervisor) "MS" else "M").getOrElse(""),
+        maxpglevels = tiles.headOption.map(_.tileParams.core.pgLevels).getOrElse(0),
         mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)),
         mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)),
         pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0),

diff --git a/generators/testchipip b/generators/testchipip