Switch RTL-sim/FPGA/VLSI flows to chisel6

build.sbt

@@ -1,5 +1,9 @@
 import Tests._
 
+val chisel6 = sys.env.get("USE_CHISEL6").isDefined
+val chiselTestVersion = if (chisel6) "6.0.0" else "0.6.0"
+val scalaVersionFromChisel = if (chisel6) "2.13.12" else "2.13.10"
+
 // This gives us a nicer handle to the root project instead of using the
 // implicit one
 lazy val chipyardRoot = Project("chipyardRoot", file("."))
@@ -11,7 +15,7 @@ val chiselFirrtlMergeStrategy = CustomMergeStrategy.rename { dep =>
     case p: Project => p.name
     case l: Library => l.moduleCoord.name
   }
-  if (Seq("firrtl", "chisel3").contains(nm.split("_")(0))) { // split by _ to avoid checking on major/minor version
+  if (Seq("firrtl", "chisel3", "chisel").contains(nm.split("_")(0))) { // split by _ to avoid checking on major/minor version
     dep.target
   } else {
     "renamed/" + dep.target
@@ -21,11 +25,13 @@ val chiselFirrtlMergeStrategy = CustomMergeStrategy.rename { dep =>
 lazy val commonSettings = Seq(
   organization := "edu.berkeley.cs",
   version := "1.6",
-  scalaVersion := "2.13.10",
+  scalaVersion := scalaVersionFromChisel,
   assembly / test := {},
   assembly / assemblyMergeStrategy := {
     case PathList("chisel3", "stage", xs @ _*) => chiselFirrtlMergeStrategy
+    case PathList("chisel", "stage", xs @ _*) => chiselFirrtlMergeStrategy
     case PathList("firrtl", "stage", xs @ _*) => chiselFirrtlMergeStrategy
+    case PathList("META-INF", _*) => MergeStrategy.discard
     // should be safe in JDK11: https://stackoverflow.com/questions/54834125/sbt-assembly-deduplicate-module-info-class
     case x if x.endsWith("module-info.class") => MergeStrategy.discard
     case x =>
@@ -35,6 +41,7 @@ lazy val commonSettings = Seq(
   scalacOptions ++= Seq(
     "-deprecation",
     "-unchecked",
+    "-Ytasty-reader",
     "-Ymacro-annotations"), // fix hierarchy API
   unmanagedBase := (chipyardRoot / unmanagedBase).value,
   allDependencies := {
@@ -82,13 +89,23 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
   new Group(test.name, Seq(test), SubProcess(options))
 } toSeq
 
-val chiselVersion = "3.6.0"
 
-lazy val chiselSettings = Seq(
-  libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion,
-  "org.apache.commons" % "commons-lang3" % "3.12.0",
-  "org.apache.commons" % "commons-text" % "1.9"),
-  addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full))
+lazy val chisel6Settings = Seq(
+  libraryDependencies ++= Seq("org.chipsalliance" %% "chisel" % "6.0.0",
+    "org.apache.commons" % "commons-lang3" % "3.12.0",
+    "org.apache.commons" % "commons-text" % "1.9"),
+  addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % "6.0.0" cross CrossVersion.full)
+)
+lazy val chisel3Settings = Seq(
+  libraryDependencies ++= Seq(
+    "edu.berkeley.cs" %% "chisel3" % "3.6.0",
+    "org.apache.commons" % "commons-lang3" % "3.12.0",
+    "org.apache.commons" % "commons-text" % "1.9"
+  ),
+  addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.6.0" cross CrossVersion.full)
+)
+
+lazy val chiselSettings = if (chisel6) chisel6Settings else chisel3Settings
 
 
 // Subproject definitions begin
@@ -97,8 +114,8 @@ lazy val chiselSettings = Seq(
 
 lazy val hardfloat = freshProject("hardfloat", file("generators/hardfloat/hardfloat"))
   .settings(chiselSettings)
-  .dependsOn(midasTargetUtils)
   .settings(commonSettings)
+  .dependsOn(if (chisel6) midasStandaloneTargetUtils else midasTargetUtils)
   .settings(
     libraryDependencies ++= Seq(
       "org.scalatest" %% "scalatest" % "3.2.0" % "test"
@@ -138,25 +155,24 @@ lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
       "com.lihaoyi" %% "sourcecode" % "0.3.1"
     )
   )
-  .settings( // Settings for scalafix
-    semanticdbEnabled := true,
-    semanticdbVersion := scalafixSemanticdb.revision,
-    scalacOptions += "-Ywarn-unused"
-  )
 lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies)
 
 
 // -- Chipyard-managed External Projects --
 
 // Contains annotations & firrtl passes you may wish to use in rocket-chip without
 // introducing a circular dependency between RC and MIDAS
+lazy val midasStandaloneTargetUtils = (project in file("tools/midas-targetutils"))
+  .settings(commonSettings)
+  .settings(chiselSettings)
 lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils")
 
 lazy val testchipip = (project in file("generators/testchipip"))
   .dependsOn(rocketchip, rocketchip_blocks)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
+val stageDir = if (chisel6) "tools/stage/src/main/scala" else "tools/stage-chisel3/src/main/scala"
 lazy val chipyard = (project in file("generators/chipyard"))
   .dependsOn(testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache,
     dsptools, rocket_dsp_utils,
@@ -169,7 +185,7 @@ lazy val chipyard = (project in file("generators/chipyard"))
     )
   )
   .settings(commonSettings)
-  .settings(Compile / unmanagedSourceDirectories += file("tools/stage-chisel3/src/main/scala"))
+  .settings(Compile / unmanagedSourceDirectories += file(stageDir))
 
 lazy val barf = (project in file("generators/bar-fetchers"))
   .dependsOn(rocketchip)
@@ -221,7 +237,7 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
-lazy val gemmini = (project in file("generators/gemmini"))
+lazy val gemmini = freshProject("gemmini", file("generators/gemmini"))
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
@@ -232,7 +248,7 @@ lazy val nvdla = (project in file("generators/nvdla"))
   .settings(commonSettings)
 
 lazy val caliptra_aes = (project in file("generators/caliptra-aes-acc"))
-  .dependsOn(rocketchip, rocc_acc_utils, testchipip, midasTargetUtils)
+  .dependsOn(rocketchip, rocc_acc_utils, testchipip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
@@ -242,21 +258,24 @@ lazy val rocc_acc_utils = (project in file("generators/rocc-acc-utils"))
   .settings(commonSettings)
 
 lazy val tapeout = (project in file("./tools/tapeout/"))
-  .settings(chiselSettings)
+  .settings(chisel3Settings) // stuck on chisel3 and SFC
   .settings(commonSettings)
+  .settings(scalaVersion := "2.13.10") // stuck on chisel3 2.13.10
   .settings(libraryDependencies ++= Seq("com.typesafe.play" %% "play-json" % "2.9.2"))
 
-lazy val fixedpoint = freshProject("fixedpoint", file("./tools/fixedpoint-chisel3/"))
+val fixedpointDir = if (chisel6) "./tools/fixedpoint" else "./tools/fixedpoint-chisel3"
+lazy val fixedpoint = freshProject("fixedpoint", file(fixedpointDir))
   .settings(chiselSettings)
   .settings(commonSettings)
 
-lazy val dsptools = freshProject("dsptools", file("./tools/dsptools-chisel3"))
+val dsptoolsDir = if (chisel6) "./tools/dsptools" else "./tools/dsptools-chisel3"
+lazy val dsptools = freshProject("dsptools", file(dsptoolsDir))
   .dependsOn(fixedpoint)
   .settings(
     chiselSettings,
     commonSettings,
     libraryDependencies ++= Seq(
-      "edu.berkeley.cs" %% "chiseltest" % "0.6.0",
+      "edu.berkeley.cs" %% "chiseltest" % chiselTestVersion,
       "org.scalatest" %% "scalatest" % "3.2.+" % "test",
       "org.typelevel" %% "spire" % "0.18.0",
       "org.scalanlp" %% "breeze" % "2.1.0",

fpga/Makefile

@@ -87,6 +87,8 @@ ifeq ($(SUB_PROJECT),arty100t)
 	FPGA_BRAND        ?= xilinx
 endif
 
+export USE_CHISEL6=1
+
 include $(base_dir)/variables.mk
 
 # default variables to build the arty example

sims/common-sim-flags.mk

@@ -4,6 +4,7 @@
 SIM_OPT_CXXFLAGS := -O3
 LRISCV=-lriscv
 
+export USE_CHISEL6=1
 
 SIM_CXXFLAGS = \
 	$(CXXFLAGS) \

vlsi/Makefile

@@ -45,6 +45,7 @@ VLSI_TOP           ?= $(TOP)
 VLSI_MODEL_DUT_NAME ?= chiptop0
 # If overriding, this should be relative to $(vlsi_dir)
 VLSI_OBJ_DIR       ?= build
+export USE_CHISEL6        = 1
 ifneq ($(CUSTOM_VLOG),)
 	OBJ_DIR          ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(VLSI_TOP)
 else