Rename testchip_fesvr to testchip_tsi

ucb-bar · Oct 9, 2020 · 0c46ed1 · 0c46ed1
1 parent 25129c2
commit 0c46ed1
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Showing 3 changed files with 4 additions and 4 deletions.
diff --git a/generators/testchipip b/generators/testchipip
diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala
@@ -83,8 +83,8 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
   }
   def resources(sim: Simulator): Seq[String] = Seq(
     "/testchipip/csrc/SimSerial.cc",
-    "/testchipip/csrc/testchip_fesvr.cc",
-    "/testchipip/csrc/testchip_fesvr.h",
+    "/testchipip/csrc/testchip_tsi.cc",
+    "/testchipip/csrc/testchip_tsi.h",
     "/testchipip/csrc/SimDRAM.cc",
     "/testchipip/csrc/mm.h",
     "/testchipip/csrc/mm.cc",

diff --git a/sims/firesim b/sims/firesim