vhdl

Star

Here are 154 public repositories matching this topic...

cocotb / cocotb

Star

cocotb: Python-based chip (RTL) verification

python test vhdl verification verilog uvm

Updated Aug 31, 2026
Python

olofk / fusesoc

Star

Package manager and build abstraction tool for FPGA/ASIC development

python package-manager fpga vhdl eda verilog reuse

Updated Aug 24, 2026
Python

siliconcompiler / siliconcompiler

Star

Modular hardware build system

asic fpga hls vhdl eda rtl verilog make synthesis cmos

Updated Aug 31, 2026
Python

olofk / edalize

Star

An abstraction library for interfacing EDA tools

Updated Aug 12, 2026
Python

JulianKemmerer / PipelineC

Star

PypelineC: A hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

python c fpga hls hardware vhdl pipelines open-source-hardware high-level-synthesis hardware-description-language fpga-accelerators fpga-acceleration fpga-programming hardware-description

Updated Aug 30, 2026
Python

FPGA-Research / FABulous

Star

An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️

python asic fpga vhdl verilog efpga

Updated Aug 25, 2026
Python

jeremiah-c-leary / vhdl-style-guide

Star

Style guide enforcement for VHDL

styleguide linting guide vhdl style beautify coding standard

Updated Jul 24, 2026
Python

suoto / hdl_checker

Star

Repurposing existing HDL tools to help writing better code

Updated Jun 21, 2026
Python

Nic30 / hwt

Star

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

simulator fpga compiler hls vhdl rtl verilog hcl codegenerator codegen systemverilog systemc uvm

Updated Aug 25, 2026
Python

kevinpt / symbolator

Star

HDL symbol generator

vhdl verilog symbol hdl

Updated Feb 2, 2023
Python

lcapossio / fpgacapZero

Sponsor

Star

fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI

fpga vhdl logic analyzer debug verilog spi jtag axi

Updated Aug 30, 2026
Python

hdl-registers / hdl-registers

Star

An open-source HDL register code generator fast enough to run in real time.

python c html asic generator fpga cplusplus register vhdl eda rtl csr axi axi-lite register-interface

Updated Aug 10, 2026
Python

Paebbels / pyVHDLParser

Star

Streaming based VHDL parser.

parser vhdl python-3 language-model

Updated Jul 15, 2024
Python

cocotb / cocotb-bus

Star

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

interface bus vhdl verilog hdl testbench cocotb

Updated Aug 24, 2026
Python

VHDL / pyVHDLModel

Star

An abstract language model of VHDL written in Python.

python dom vhdl abstract language-model

Updated Aug 25, 2026
Python

oddball / ipxact2systemverilog

Star

Translates IPXACT XML to synthesizable VHDL or SystemVerilog

vhdl verilog ip-xact systemverilog

Updated Jan 28, 2026
Python

suoto / vim-hdl

Star

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

productivity vhdl vim-plugins verilog xilinx syntastic syntax-checker altera systemverilog modelsim

Updated Jun 1, 2021
Python

mbuesch / crcgen

Star

Generator for CRC HDL code (VHDL, Verilog, MyHDL)

vhdl verilog crc crc-algorithms crc-calculation crc32 myhdl

Updated Oct 13, 2023
Python

tsfpga / tsfpga

Star

A flexible and scalable development platform for modern FPGA projects.

asic fpga ci simulation test vhdl build-automation eda test-automation rtl verilog xilinx synthesis vivado systemverilog implementation vunit

Updated Aug 10, 2026
Python

Nic30 / hwtLib

Star

hardware library for hwt (= ipcore repo)

fpga vhdl rtl verilog hardware-designs

Updated Aug 24, 2026
Python

Improve this page

Add a description, image, and links to the vhdl topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the vhdl topic, visit your repo's landing page and select "manage topics."

Learn more