Project done for my B.Tech course on Formal Methods for System Verification
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Updated
Oct 25, 2021
Project done for my B.Tech course on Formal Methods for System Verification
Simulating traffic controller sequence at Thapathali intersection using Xilinx and 8051
Sensor-aware 4-road traffic light controller using Finite State Machine in Verilog. Dynamically manages traffic flow with priority-based signal allocation, timer-controlled phase transitions, and real-time traffic monitoring for smart city applications.
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