Single-cycle 32-bit MIPS CPU designed and simulated in Logisim, built for the Computer Architecture Lab (LCOM 3010) at the Islamic University of Gaza. Supports lw, sw, add, sub, and, or, slt, beq, and j.
A simple risc-v single-core CPU design written in Verilog, developed for learning and practicing computer architecture and hardware description languages.
CO224 Computer Architecture Labs - 8-bit Single-Cycle Processor Implementation .
MIPS Processor Implementations (VHDL) | This repository contains multiple implementations of the MIPS (Microprocessor without Interlocked Pipelined Stages) architecture using VHDL. The project is designed for educational and academic purposes, helping students understand CPU architecture and datapath/control design. It includes Single-Cy
16-bit Single-Cycle CPU designed and verified in Verilog RTL, featuring a custom ISA, 8-bit ALU, register file, instruction memory, branching, jumps, and ModelSim-based verification.
A single-cycle RISC-V CPU implemented in Verilog, with arithmetic, memory, branch, and jump instructions verified using Icarus Verilog and GTKWave.
32-bit Single-Cycle RISC-V (RV32I) CPU built completely from scratch using basic logic primitives and universal NAND gates in Logisim-Evolution. Features full datapath, ALU, Control Unit, 32-register file, Data Memory, and support for R-type, I-type, S-type, and B-type instructions.
32-bit single-cycle CPU with control unit — Logisim simulation for Computer Organization & Architecture.
Formally verified, synthesis-ready 8-bit RISC CPU in Verilog. Optimized for efficient hardware implementation.
To associate your repository with the single-cycle-cpu topic, visit your repo's landing page and select "manage topics."