RV32IM RISC-V CPU core with a full UVM verification environment and ISA-compliance via Spike (DPI-C): constrained-random, SVA, coverage, Python debug tools, and CI.

This is an RV32_IM riscv cpu core. Its a non-pipelined core with MULW instruction alone from M extension.

Attempt at building entirely from scratch a RISC-V SoC for self-education purposes.