RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

A curated collection of RISC-V assembly experiments for the Ripes simulator — the repository provides ready-to-run labs that illustrate key CPU design and performance concepts. Each experiment comes with explained theory, .asm code, and expected metrics, making it ideal as a learning resource or teaching toolkit.

Repositório para armazenar os códigos de linguagem de montagem assembly da matéria de Arquitetura e Organização de Computadores da Universidade Federal de Uberlândia

RISC-V implementation for Parallel Computer Architecture class.

A collection of RISC-V assembly programs I wrote for use with RARS