A curated collection of RISC-V assembly experiments for the Ripes simulator — the repository provides ready-to-run labs that illustrate key CPU design and performance concepts. Each experiment comes with explained theory, .asm code, and expected metrics, making it ideal as a learning resource or teaching toolkit.
riscv performance-analysis computer-architecture risc-v risc-processor riscv32 cache-memory assembly-programming processor-simulation ripes cpu-pipeline educational-labs
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Updated
Dec 6, 2025 - Assembly