Verilog Multiplier Implementation

The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.

Character typing game using TypeScript

Design and Analysis of an FPGA-based Wallace Multiplier.

Useful VHDL scripts for hardware description.

Digital design project for a simple integer multiplier using Booth's multiplication algorithm made through ASM design method

Bingo game with score

8 bit multiplier Verilog code

A 32-bit Signed Vedic Multiplier created using Verilog HDL utilising Vedic Mathematic Sutras formed using Carry Lookahead Adders as the basic building blocks.

Different Multipliers code in VHDL and Comparison

idle game thingy.

Verilog Codes for various digital circuits for labs at IIT Ropar, basic gates, adders & subtractors (half & full), ripple adders, multipliers and code converters.

Parameterized and 4-bit carry save multiplier design

Approximate Multipliers of 8bit and 16bit operands, built with approximate compressors.

Approximate layers - TensorFlow extension