This project implements a 10 Gigabit Ethernet (10GbE) interface using the Kintex-7 GTX transceivers on the ALINX AX7325B board. It uses the open-source [verilog-ethernet](https://github.com/alexforencich/verilog-ethernet) library for the MAC/PHY layers.
A complete custom implementation of the 10GBASE-R Physical Layer (PHY) in VHDL. This implementation provides full control over the 10 Gigabit Ethernet physical layer without relying on encrypted vendor IP.
Implements multi-protocol market data parsing supporting NASDAQ (UDP/MoldUDP64), ASX (TCP/SoupBinTCP), and B3 Brazilian Exchange (UDP/SBE) market data feeds. Integrates with Project 33's 10GBASE-R PHY for 10GbE reception and outputs parsed messages via Aurora to FPGA2 (order book engine).
This KiCad project implements the PCB design for the Standalone 3-FPGA Trading Appliance
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