First steps with the Sipeed Tang Primer 20k FPGA.
-
Updated
May 5, 2025 - Verilog
#
gowin-eda
Here are 3 public repositories matching this topic...
Two-way ASCII character transmission via SPI with display output
-
Updated
Jul 1, 2025 - Verilog
This project implements a BCD (Binary-Coded Decimal) converter that reads DIP switch input and controls a 7-segment display, showing digits 0–8 or ‘E’ for invalid combinations.
-
Updated
May 5, 2025 - Verilog
Improve this page
Add a description, image, and links to the gowin-eda topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the gowin-eda topic, visit your repo's landing page and select "manage topics."