This repository contains Verilog/C examples with Tang Nano (4K/9K/20K) and Zybo Z7
-
Updated
Aug 12, 2025 - F#
#
gowin-eda
Here are 5 public repositories matching this topic...
First steps with the Sipeed Tang Primer 20k FPGA.
-
Updated
May 5, 2025 - Verilog
Two-way ASCII character transmission via SPI with display output
-
Updated
Jul 1, 2025 - Verilog
This project implements a BCD (Binary-Coded Decimal) converter that reads DIP switch input and controls a 7-segment display, showing digits 0–8 or ‘E’ for invalid combinations.
-
Updated
May 5, 2025 - Verilog
This repository compiles notes, fixes, and configuration files related to bugs and issues encountered during the installation and use of various software tools on both Linux and Windows platforms.
zynq xilinx altera de1-soc questasim xilinx-fpga xilinx-vivado quartus-prime altera-fpga tang gowin altera-quartus tang-primer gowin-eda monitor-program
-
Updated
Aug 17, 2025
Improve this page
Add a description, image, and links to the gowin-eda topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the gowin-eda topic, visit your repo's landing page and select "manage topics."