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Language: SystemVerilog
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barannmeisterr / 32-Bit-ALU-Design

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This project is a 32-bit Arithmetic Logic Unit (ALU) designed in SystemVerilog as part of a MIPS microprocessor simulation. The ALU supports various arithmetic and logical operations and includes a custom-built 32-bit full adder, one 2-to-1 MUX, one 4-to-1 MUX, one AND gate , one OR gate and the Zero Extend Logic

verilog fulladder systemverilog mux logic-gates alu multiplexer computerorganization inverter arithmetic-logic-unit
  • Updated Nov 2, 2024
  • SystemVerilog

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