💯 CSPostgraduate 计算机考研 408 专业课资料及真题资源

CSE GATE - 2020

Storing data in 16-bit multilevel Direct Mapped, Associative, N-way Set Associative cache memory

Marmara University 3rd year course

Computer Organization

Created a virtual machine including CPU, assembler, and RISC from scratch using JAVA

Computer Systems Organization

Computer Organization (Assembly and Verilog Languages) MIPS Assembly, Syscalls, Processor, Verilog, ALU module, Instructions, Memory module, Register module, FPGA

计算机组成课程笔记

Tic-tac-toe is played on a three-by-three grid by two players, who alternately place the marks X and O in one of the nine spaces in the grid.

nand2tetris

This project is a 32-bit Arithmetic Logic Unit (ALU) designed in SystemVerilog as part of a MIPS microprocessor simulation. The ALU supports various arithmetic and logical operations and includes a custom-built 32-bit full adder, one 2-to-1 MUX, one 4-to-1 MUX, one AND gate , one OR gate and the Zero Extend Logic

This repository is used to save the lecture powerpoint, assignments and labs.

Contains all projects from my computer science classes at LSU