fsm-design

Lusan: Control Plane for Designing and Debugging Areg-Based Distributed Systems

This repository contains all the verilog codes of combinational, sequential and fsm based circuits with 3 levels of modelling ( dataflow, structural, behavioral ) using Xilinx Vivado 2020.2 software.

Digital Alarm Clock in Verilog HDL | FSM | ModelSim | Intel Quartus Prime | FPGA RTL Design

FPGA-based solar-powered EV charging station with FSM-based charge control and MPPT implementation for efficient energy management. Designed in Verilog with ModelSim validation. Achieves real-time control, reduced peak demand, and improved battery health; accepted as a CRC Press/Taylor & Francis book chapter.

Low-power fixed-point Softmax processing unit with LUT-based exponentiation and an 8-stage pipelined Mitchell logarithmic divider. Designed in Verilog and implemented on TSMC 180nm using Cadence tools. Achieves 1 output/cycle throughput and 8.9× speedup over sequential division. Patent under review.

Hardware maze game built in Verilog on the DE1-SoC FPGA, featuring FSM-based control, PS/2 input, VGA rendering, and ROM-based collision detection.

Practical hardware experiments, Proteus/Logisim schematics, and ASM controller designs for the CE-206 (Digital Logic Design Laboratory) course using standard TTL 74xx ICs.