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These labs were conducted during our Digital systems elective course were we were instructed to build Verilog code for specific logic design and verify it on Quartus modalism and on the FPGA. Skills developed: writing Verilog code structurally and behaviorally, testing, simulation, writing test benches and using the FPGA
A Pseudo-Random Noise Sequence Generator VHDL implementation to synthesize on a Zync FPGA for the Digital Systems Design course of University of Pisa, 2019.
This repository contains all the necessary Verilog code and supporting files to synthesize the 8-bit soft-core processor on an FPGA. The code is well-commented, following best practices in digital design to ensure clarity and maintainability.
PongFPGA: Experience the classic Pong game reimagined with FPGA tech! 🕹️ Dive into the world of hardware programming for thrilling entertainment and education! 🚀🎮