Verilog Implementation of Run Length Encoding for RGB Image Compression

基于易灵思Ti60F225开发板和MT9M001双目摄像头，使用Verilog语言完成的双目拼接项目。摄像头输入图像数据后，在使用FAST计算图像特征点的同时，构建滑动窗口计算图像各个像素点的BRIEF描述符，完成后根据BRIEF描述符对两幅图像上的特征点进行暴力匹配，最后通过匹配结果计算拼接参数，完成图像的拼接。

ES-203 Computer Organization & Architecture CNN on FPGA board

Router 1 x 3 verilog implementation

FPGA Guide

RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga

My experiments with Nexys4 DDR Artix-7 FPGA Board

UART - RTL Design and Verification

Digital Audio Noise Filtering with MATLAB and Verilog This project implements a complete end-to-end system for detecting and filtering noise from real-world audio using a combination of MATLAB signal processing and Verilog hardware design. Starting from spectral analysis and filter synthesis in MATLAB, it proceeds to fixed-point audio formatting,

⚡️Code release for Accelerating CNNs on FPGA [Published in Research in Intelligent and Computing in Engineering 2020]

probable journey of RTL coding ft. Chandra Prakash

Collection of my projects that was made as a part of Warsaw University FPGA course

This project proposes to demonstrate the capabilities and scope of Verilog HDL by implementing the control system of an automatic washing machine. The above mentioned objective by implementing the Control System of an automatic washing using the Finite State Machine model. The washing machine control system generates all the control signals requ…

A simplified RISC-V processor implemented in Verilog and deployed on the DE-2 SoC FPGA board.

Exploring both MATLAB and Vivado Verilog in designing a Direct Digital Synthesizer (DDS) system with a FIR low-pass filter. This project goes into digital system design, signal processing, and hardware implementation.

Vertex 6 FPGA GTx Transciever Simulation in Xilinx ISE using Xilinx IP Core

A collection of practical sessions exploring FPGA programming and MIPS-based systems using the ALTERA Cyclone V DE-1 SoC board.

𝗠𝗶𝗻𝗶𝗠𝗜𝗣𝗦 | 𝗥𝗜𝗦𝗖 𝗣𝗿𝗼𝗰𝗲𝘀𝘀𝗼𝗿 𝗗𝗲𝘀𝗶𝗴𝗻 | CS39001 𝗖𝗼𝘂𝗿𝘀𝗲 𝗣𝗿𝗼𝗷𝗲𝗰𝘁

Welcome to the repository for **Exercise 3 of the AI Systems Course** at the **University of Tehran**. This project focuses on designing and implementing a lightweight, efficient **processing element (PE)** for performing operations of neurons in a **multi-layer perceptron (MLP)** using Verilog.

A FPGA implementation of Ben Eater's SAP-1 computer using the Digilent's BASYS 3 board.