TURBOdeb #xohw19-157 #TuringBombe #Enigma

Develop DMA acceleration of the system that performs linear computing functions, Y = AX + B, large amounts of data.

A framework for Automated Design Space Exploration

FPGA with Xilinx Vitis HLS and ZYNQ board. AXI and VHDL: Simple Multiplier, AXI and VHDL: DoGain

A heterogeneous implementation (SW/HW) of an image processing algorithm running on a Yocto-linux OS

A parallel implementation of an Image Steganography Decode in simulation on a Nexys-A7 FPGA. The decoder expects images encoded with the least significant bit decoder.

Enable PYNQ on the Avnet MicroZed boards

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

🏄 Custom IP for vector operations

Janus astrophysics Simulator implemented on ZU19EG Ultrascale+

Smart Automation Controller for Precision Agriculture

Janus Algorithm in C++ version without FPGA acceleration.

A FPGA Based Square Root Approximation Coprocessor

Projekt zaliczeniowy w ramach przedmiotu "Systemy Cyfrowe". Projekt miał na celu stworzenie układu DSP do pomiaru odległości za pomocą odbitego światła lasera. Wykonano układ który można finalnie uruchomić na płytce Cyclone IV Altera (model EP4CE6E22), który można sterować bezpośrednio na płytce. Objaśnienie projektu znajduje się w załączonym do…

Predicting 3D human pose from single image using a VCK5000 Versal Development Card

A lightweight cloudFPGA prototype for processor simulation. It provides online scalable route resources with only open source synthesis toolset.

Blake2 RTL implementation

Implementation of a somewhat homomorphic encryption system using an FPGA hardware accelerator. This project was part of my bachelor's thesis at KIT and developed in four months.

This repository contains the design and implementation of a Spiking Neural Network (SNN) Processor. Spiking Neural Networks are a biologically-inspired class of artificial neural networks, where neurons communicate by sending discrete spikes.

Reconfigurable Digital Systems HRY591-project.