Convolutional accelerator kernel, target ASIC & FPGA
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Updated
Apr 10, 2023 - Verilog
Convolutional accelerator kernel, target ASIC & FPGA
Small-scale Tensor Processing Unit built on an FPGA
The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design"
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
TCP/IP and UDP/IP protocol stack off-loading
Co-processor for whole genome alignment
Network Packet classification on FPGA
Blake2 RTL implementation
This repository contains the design and implementation of a Spiking Neural Network (SNN) Processor. Spiking Neural Networks are a biologically-inspired class of artificial neural networks, where neurons communicate by sending discrete spikes.
Projekt zaliczeniowy w ramach przedmiotu "Systemy Cyfrowe". Projekt miał na celu stworzenie układu DSP do pomiaru odległości za pomocą odbitego światła lasera. Wykonano układ który można finalnie uruchomić na płytce Cyclone IV Altera (model EP4CE6E22), który można sterować bezpośrednio na płytce. Objaśnienie projektu znajduje się w załączonym do…
A heterogeneous implementation (SW/HW) of an image processing algorithm running on a Yocto-linux OS
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