FIR implemention with Verilog

The Design and Implementation of a Pulse Compression Filter on an FPGA.

Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual files. Download the project and run the main project file.

Design and Validation of a Customizable 50th-Order Low-Pass FIR Filter. Transitioning from MATLAB Modeling to Verilog RTL Design and simulation Testing.

A pipelined Symmetric FIR (Finite Impulse Response) filter implementation in Verilog HDL.

Design and FPGA Implementation of FIR Filter using MAC (Multiplier-Accumulator) on FPGA (Artix 7)