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afzalamu/README.md

Hello, I'm Afzal Malik.👋

Welcome to my GitHub profile! I'm a passionate VLSI engineer with interest in designing circuits and systems. My interests lie in both the analog and digital domains of VLSI, where I continually strive to innovate and improve.

🖥️ Skills, Tools & Technologies

Cadence Virtuoso Xilinx Vivado Verilog HDL LT Spice Electric VLSI Circuit Design FPGA OPENLANE Python C Programming Microsoft Office

🎓 Internship

  • Analog Circuit Design Intern (June - July 2023)
    • Mentor: Dr. GS Javed, Analog Design Manager @Intel, Bangalore, India
    • Description: Designed basic building blocks of Analog Integrated Circuits including common-source amplifier, source follower amplifier, single-stage operational amplifier, two-stage operational amplifier, and filters using the gm over Id methodology.

📚 Conference Publications

  • A 5GHz Gain-Bandwidth Op-Amp in 180nm technology (May 2024)

📈 Projects

  • Design and FPGA Implementation of Neural Network based Digit Recognition System (Jan - May 2024) :

    • Description: – Design of software model of Neural Network for Handwritten Digit Recognition system using Python. Hardware realisation of the neural network using Verilog HDL, validating behavioural, Post synthesis & Post Implementation Simulations and then ANN is implemented on FPGA.
    • Tools Used: Xilinx Vivado, VS Code | FPGA Board: NEXYS A7 I Languages: Verilog HDL & Python

  • Design, simulation and layout of Two-Stage Operational Amplifier (June - July 2023) :

    • Description: Utilized Gm/Id methodology to design and simulate a Two-Stage Operational Amplifier in the 180 nm technology for the specifications: Gain >1000, Gain Bandwidth Product (GBW) > 1GHz, and Phase Margin of 50.
    • Tools Used: LT Spice, Analog Designer Toolbox (ADT), Electric Binary.

  • Design and Analysis of CMOS Inverter using CMOS 180nm Technology (Nov 2022) :

    • Description: explored MOSFET models for TSMC180nm, Analyzed strong 0/1 and weak 1/0 logic configurations through simulation. Designed CMOS Inverter, and analysed its voltage transfer characteristics and key design parameters like VOH, VOL, VIH, VIL, and the switching threshold, with its layout using Electric Binary.
    • Tools Used: LT Spice, Electric Binary.

🤝 Connect With Me

My Portfolio LinkedIn Email

Pinned Loading

  1. FIR-Filter-using-MAC FIR-Filter-using-MAC Public

    Design and FPGA Implementation of FIR Filter using MAC (Multiplier-Accumulator) on FPGA (Artix 7)

    Verilog

  2. Analog-Design-Internship Analog-Design-Internship Public

    This 6 Week summer internship, organized by the Engineering Design and Implementation Club (Edic) in collaboration with the Department of Electronics Engineering at Aligarh Muslim University, offer…

    AGS Script 1 1

  3. Design-of-two-stage-operational-amplifier-at-180nm-Technology Design-of-two-stage-operational-amplifier-at-180nm-Technology Public

    This project contains the design of two stage operational amplifier at 180nm Technology using gm over Id methodology for UGB 1GHz

    AGS Script 2

  4. Half-Adder-Schematic-to-GDS2 Half-Adder-Schematic-to-GDS2 Public

    Half Adder Schematic to GDS2 using GPDK90 in Cadence

  5. CMOS-Inverter-Design-and-GDSII-Generation-using-Cadence-Virtuoso-GPDK90- CMOS-Inverter-Design-and-GDSII-Generation-using-Cadence-Virtuoso-GPDK90- Public

    This repository contains the design and analysis of a CMOS inverter using Cadence Virtuoso with GPDK90 technology. The project includes schematic and layout design, pre-layout and post-layout simul…

    1

  6. XOR-gate-design-simulation-and-layout-using-180nm-Technology-LTSpice-ElectricBinary XOR-gate-design-simulation-and-layout-using-180nm-Technology-LTSpice-ElectricBinary Public

    This repository showcases the comprehensive design, simulation, and layout implementation of a CMOS XOR gate using TSMC 180nm technology. Originating from the coursework of ELC3611 VLSI Design & Te…

    AGS Script 1