dpretet / async_fifo Sponsor Star 384 Code Issues Pull requests A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain Updated Sep 16, 2025 Verilog
aniketnk / circular-queue-verilog Star 17 Code Issues Pull requests Implementation of a circular queue in hardware using verilog. register hardware verilog fifo-queue circular-queue fifo-buffer Updated Mar 22, 2019 Verilog
samiyaalizaidi / FIFO-In-Verilog Star 3 Code Issues Pull requests Implementation of a FIFO structure for Digital Systems | Written in Verilog HDL vivado verilog-hdl fifo-queue fifo-buffer digital-system-design Updated Mar 26, 2024 Verilog
pranavanantharam / FIFO-Memory Star 3 Code Issues Pull requests FIFO Memory Implementation using Verilog fifo-queue xilinx-vivado Updated May 16, 2020 Verilog
gnalexandridis / FIFO_HUA-MCA-2016-2017 Star 1 Code Issues Pull requests This is a simple FIFO queue implementation in Verilog for the Modern Computer Architectures course (2016-2017) of Harokopio University. verilog gtkwave fifo-queue Updated Jun 16, 2018 Verilog