This repository contains the design and implementation of a 4-bit Mealy Machine-based Overlapping Sequence Detector for detecting the sequence "1001" using 90nm CMOS technology and simulated in Cadence Virtuoso. The design employs SISO registers and master-negative edge-triggered D flip-flops within a Mealy machine architecture.

RTL Designs along with testbenches to verify them written in Verilog. Icarus Verilog an open source simulator was used for simulations.

FIFO buffer library. Written and verified in SystemVerilog. Can be synthetised in ASIC or FPGA.

a quick interface to any digital device that features magazines as a product

Educational repo for storing my practice sessions with digital systems as well as solutions to online courses or university courses I take. These implementations are done in VHDL or Verilog.

Computer Organization and Digital Design Projects - CS1050 - Semester 2

For all the fidget spinneteers out there

VHDL controller for dynamic protocol switching (CAN, LIN, FlexRay).

Took a module on Digital Design Fundamentals during my year 2 of my undergraduate studies of Electronic Circuits done using VHDL and Verilog, with a final project on FPGA Programmed Flappy Bird Gaming System using Sound and Light effects.

A slot machine created in System Verilog. It was built, simulated, synthesized, and implemented in Vivado, for use on the Xilinx Basys 3 board.

Digital Design Timing Constraints

Basic digital lock system for safes, employing logic gates 🔐

4 bit divider design using first divider algorithm

Школа инженера от DigitalDesign

This repository contains different modules which execute arithmetic operations.

Miscellaneous stuff from the NDSU Digital Design Class

PWM module using verilig HDL in XILINX ISE

This repository contains a few useful Verilog modules

VHDL tutorial

5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and main memory.