TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems

A small and simple 8-bit CPU built in Logisim. The project also includes an assembler and a manual for those who want to learn how a processor works.

A software simulator of how an OS might schedule processes

Tera - A simulated ternary (base 3) CPU, assembly language, assembler and decompiler. Uses trytes made up of 9 trits rather than bytes of 8 bits.

Implementation of Utility based cache partitioning research paper in Champsim simulator

Simulating the architecture of a computer in the terminal (Assembler + Simulator)

A Y86-64 processor simulator written in JavaScript (Node.js) and C++11

A C++ command line program that simulates a custom CPU to which one can load instructions in a custom assembler language and see the registries' changes.

A simple implementation of RISC-V CPU simulator

A binary port of Tera

An Object-Oriented CPU Simulator implemented in C++ using the Factory pattern 🏭 💻 (2016)

C++ library to simulate a MIPS32 CPU.

implementarion of a cpu risc

Реализация работы процессора

The main purpose of this project is to understand MIPS Assembly language. The input of this program is a file consisting sequence of MIPS instructions in binary. Software simulates behaviour of MIPS CPU by reading instructions and changing values of registers. At the end program prints out the current value of the registers, which matcheswith th…