SystemRDL / PeakRDL Star 173 Code Issues Pull requests Control and status register code generator toolchain asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model Updated Dec 3, 2025 Python
hdl-registers / hdl-registers Star 82 Code Issues Pull requests Discussions An open-source HDL register code generator fast enough to run in real time. python c html asic generator fpga cplusplus register vhdl eda rtl csr axi axi-lite register-interface Updated Feb 2, 2026 Python
bugratufan / axion-hdl Star 9 Code Issues Pull requests Discussions Axion-HDL: Automated AXI Register Space Generation Tool register vhdl axi axi4-lite Updated Feb 5, 2026 Python
aignacio / jtag_axi Star 4 Code Issues Pull requests JTAG to AXI master jtag axi jtag-adapter Updated Dec 14, 2025 Python
mjh-design / verilog-axis Star 0 Code Issues Pull requests Verilog AXI stream components for FPGA implementation ip axi Updated Feb 17, 2023 Python