awesome-opensource-hardware

A curated list of awesome open source hardware tools, generators, and reusable designs.

• Categorized
• Alphabetical (per category)
• Requirements
  • link should be to source code repository
  • open source projects only
  • working projects only (not WIP/rusty)
• One tag line sentence per project.

Table of Contents

Compilers

• Build Systems
• Digital
• FPGA
• Layout

Design Tools

• Analog
• Board
• Chip Layout
• Digital
• Documentation
• FPGA
• Registers

Verification

• Analog
• Benchmarks
• Digital
• Waveform Viewers

Designs & Generators

• Accelerators
• Analog Circuits
• Chip Packages
• Boards
• Connectivity
• CPUs
• FPGA Architectures
• Libraries
• Memory
• Systems

Compilers

Build Systems

• bazelhdl
  • Bazel based hdl build system
• bender
  • Dependency management tool for hardware projects.
• chipyard
  • Agile RISC-V SoC Design Framework.
• cocoon
  • An infrastructure for integrated EDA
• edalize
  • An abstraction library for interfacing EDA tools.
• fusesoc
  • Package manager and build abstraction tool for FPGA/ASIC development.
• hammer
  • Agile physical design component part of UC Berkeley Chipyard framework.
• hwtBuildsystem
  • Library of utils for interaction with the vendor tools.
• legoHDL
  • Command line HDL package manager and development tool.
• mflowgen
  • Build-system generator for ASIC and FPGA design-space exploration.
• siliconcompiler
  • Build system that automates translation from source code to silicon.

Digital Compilers

• abc
  • System for sequential logic synthesis and formal verification
• act
  • Asynchronous circuit compiler tools
• amaranth
  • Python based hardware design framework
• bsc
  • Compiler, simulator, and tools for the Bluespec Hardware Description Language
• calyx
  • Intermediate language and infrastructure compilers that generate custom hardware accelerators
• chisel
  • Scala based hardware description language
• circt
  • Circuit IR Compilers and Tools
• clash
  • Haskell to VHDL/Verilog/SystemVerilog compiler
• cocotbext-axi
  • AXI interface modules for Cocotb
• cocotbext-pcie
  • PCI express simulation framework for Cocotb
• coreir
  • LLVM-style hardware compiler with first class support for generators
• dfiant
  • Dataflow Hardware Description Language
• Fault
  • Design-for-testing (DFT) Solution
• firrtl
  • Intermediate Representation for RTL
• gamma
  • Optimizes mapping of DNN models on DNN Accelerators
• halide
  • Language for fast, portable data-parallel computation
• halide-to-hardware
  • Hardware generator combining halide and coreir
• hdlconvertor
  • Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTL4
• hs-to-coq
  • Convert Haskell source code to Coq source code
• livehd
  • Infrastructure for live interactive synthesis and simulation
• llhd
  • Intermediate representation for digital circuit descriptions
• lsoracle
  • Famework built on EPFL logic synthesis libraries.
• lstools
  • Showcase examples for EPFL logic synthesis libraries
• kami
  • Platform for High-Level Parametric Hardware Specification and its Modular Verification
• magma
  • Python based hardware design language
• matchlib
  • Synthesizable SystemC/C++ library of commonly-used hardware functions
• matchclib_connections
  • Synthesizable SystemC library implementing latency-insensitive channels
• mockturtle
  • C++ logic network library
• myhdl
  • Python based hardware description and verification language
• naja
  • Structural Netlist API (and more) for EDA post synthesis flow development
• netlist-paths
  • A library and command-line tool for querying a Verilog netlist
• panda-bambu
  • High level synthesis (HLS) C/C++ framework
• pipelinec
  • C-like hardware description language (HDL) with automatic pipelining
• pygears
  • Python based hardware design framework
• pymtl3
  • Python hardware generation, simulation, and verification framework
• pyrtl
  • Python integrated design and simulation framework
• pysysc
  • Python package to make SystemC usable from Python
• pyverilog
  • Python design toolkit for Verilog HDL
• rohd
  • Dart based framework for describing and verifying hardware
• sandpiper-saas
  • A CLI to Redwood EDA, LLC's free SandPiper™ TL-Verilog compiler microservice
• silice
  • Language that simplifies prototyping and writing algorithms on FPGA architectures
• skidl
  • SKiDL is a module that extends Python with the ability to design electronic circuits
• slang
  • Library for lexing, parsing, type checking, and elaborating SystemVerilog code
• sodaopt
  • Optimizer leveraging mlir to extract, optimize, translate HLSinto LLVM IR
• spinalhdl
  • Scala based HDL
• spydrnet
  • Framework for analyzing and transforming Verilog netlists
• surelog
  • SystemVerilog IEEE 2017 Pre-processor, Parser, Elaborator, UHDM Compiler
• sv-parser
  • SystemVerilog IEEE 1800-2017 parser library
• sv2v
  • SystemVerilog to Verilog conversion
• systemc
  • SystemC system design and verification language that spans hardware and software
• systemc-compiler
  • Translates synthesizable SystemC to synthesizable Verilog
• uhdm
  • Universal object model for IEEE SystemVerilog designs
• verible
  • Suite of SystemVerilog developer tools, including a parser, style-linter, and formatter
• veriloggen
  • Mixed-Paradigm Hardware Construction Framework
• verik
  • Kotlin based hardware description language
• Vlsir
  • Interchange formats for chip design
• xls
  • Google framework for hardware synthesis
• yosys
  • Yosys Open SYnthesis Suite

FPGA Compilers

• amf-placer
  • Timing-driven analytical mixed-size FPGA placer
• dreamplacefpga
  • Analytical Placer for Large Scale Heterogeneous FPGA
• flowtune
  • FPGA synehsis and PNR optimizer
• nextpnr
  • FPGA place and route tool
• vtr
  • FPGA place and route tool

Layout Compilers

• align
  • Automatic layout generator for analog circuits
• bag
  • Berkeley analog layout generator
• bigspicy
  • Tool for merging circuit descriptions
• dreamplace
  • Deep learning toolkit-enabled VLSI placement
• Layout21
  • Integrated Circuit Layout
• magical
  • Machine Generated Analog IC Layout
• openroad
  • Complete RTL2GDS platform

Design Tools

Analog Design

• OpenPLC_Editor
  • IDE capable of creating programs for the OpenPLC Runtime
• oregano
  • Schematic capture and circuit simulator
• qucs_s
  • Integrated circuit simulator with Graphical User Interface
• xschem
  • Schematic editor for VLSI/Asic/Analog custom designs

Board Design

• boardview
  • Reads KiCAD PCB layout files and writes ASCII Boardview files
• cuflow
  • Experimental procedural PCB layout program
• datasheet-scrubber
  • Utility that scrubs PDF datasheets/documents in order to extract key circuit information
• freecad
  • 3D parametric CAD for building models of components for KiCad 3D preview (also enclosures)
• kicad
  • Board design framework
• pcbflow
  • Python based Printed Circuit Board (PCB) layout and design package based on CuFlow

Chip Layout

• chip_art
  • Convert an image to a GDS format for inclusion in a zerotoasic project
• coriolis
  • RTL2GDS toolchain for mature nodes
• gds3d
  • Reads GDSII layout and renders in 3D.
• gdsfactory
  • Python package to generate GDS layouts.
• gdstk
  • C++/Python library for creation and manipulation of GDSII and OASIS files.
• gdspy
  • Python module for creating GDSII stream files, usually CAD layouts.
• klayout
  • Layout viewer
• lclayout
  • Layout generator for CMOS standard-cells
• netgen
  • LVS tool for comparing SPICE or verilog netlists
• phidl
  • Python GDS layout and CAD geometry creation
• probe3.0
  • Process/design DTCO path finding technology

Digital Design

• circuitgraph
  • Tools for working with circuits as graphs in python
• makerchip-app
  • Launches Makerchip.com as a virtual desktop application
• verilog-mode
  • Popular free Verilog mode for Emacs

Documentation

• graphviz
  • Python library for graph cration and rendering in DOT language
• memory-layout-diagram
  • Diagrams for memory map layouts
• netlistsvg
  • draws an SVG schematic from a JSON netlist
• pcbdraw
  • Convert KiCAD board into 2D drawing suitable for pinout diagrams
• pinion
  • Generate interactive Diagrams for your PCBs
• pinout
  • Python package that generates hardware pinout diagrams as SVG images
• sphinx
  • Document builder
• sphinx-verilog-domain
  • Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
• sphinxcontrib-hdl-diagrams
  • Sphinx plugin to automatically generate diagrams from RTL.
• symbolator
  • HDL symbol generator
• undulate
  • Python compatible wavedrom module with extensions and console rendering support
• wavedrom
  • Digital timing diagram rendering engine
• wavedrompy
  • Python comptabled Wavedrom module

FPGA Design

• 1st-class
  • Framework for FPGA cloud accelerators
• byteman
  • Bitstream relocation and manipulation tool
• icestudio
  • Visual editor for open FPGA boards
• foedag
  • Framework Open EDA Gui
• openfpgaloader
  • Universal utility for programming FPGA
• rphax
  • Automation flow to develop and prototype hardware accelerators on Xilinx FPGAs
• virtual-fpga-lab
  • FPGA development in your browser

Register Design

• gen_registers
  • Python based tool for generating hardware registers and their associated files
• rggen
  • Configuration and status register generator
• systemrdl
  • Generic compiler front-end for Accellera's SystemRDL 2.0 register description language

Verification

Analog Verification

• adc-eval
  • Python tools for ADC performance analysis
• anasysmod
  • Framework for FPGA emulation of mixed-signal systems
• cvc
  • CVC: Circuit Validity Checker.
• devsim
  • TCAD Semiconductor Device Simulator
• eesim
  • Browser-based SPICE circuit simulator
• lctime
  • Library cell characterization
• hotspot
  • Thermal modeling tool for use in architectural studies
• ngspice
  • Spice simulator
• msdsl
  • Automatic generation of real number models from analog circuits
• OpenPLC_v3
  • OpenPLC Runtime version 3
• OpenVAF
  • Next generation Verilog-A compiler
• pact
  • Thermal Simulator
• pyaedt
  • Ansys AEDT Python Client Package
• pydpf-core
  • Ansys core processing framework
• pyfluent
  • Ansys interface to Ansys Fluent
• pymapdl
  • Ansys interface to MAPDL
• pyspice
  • Python interface for ngspice and xyce
• SimulIDE
  • SimulIDE is a simple real-time electronic circuit simulator
• svreal
  • Synthesizable real number library in SystemVerilog (fixed & floating point formats)
• xyce
  • Parallel spice simulator from Sandia national labs

Benchmarks

• bsg_pipeclean_suite
  • Collection of designs used to stress test new CAD flows
• corescore
  • Benchmark for FPGAs and their synthesis/P&R tools
• epfl-benchmarks
  • Combinational Benchmark Suite for logic synthesis
• opdb
  • Princeton design benchmark generators
• rdf-2020
  • IEEE CEDA eda benchmark flow
• sv-tests
  • SystemVerilog compliance test suite

Digital Verification

• awsteria_infra
  • Middleware for AWS hosted FPGA applications
• boolector
  • SMT solver for the theories of fixed-size bit-vectors, arrays and uninterpreted functions.
• champsim
  • Trace-based simulator for a microarchitecture study.
• cocotb
  • Coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
• cvc5
  • SMT automatic theorem prover
• dromajo
  • RISC-V RV64GC functional emulator
• essent
  • High-performance FIRRTL (Chisel) simulator
• firesim
  • FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud
• frame
  • Fast Roofline Analytical Modeling and Estimation
• fstdumper
  • Verilog VPI module to dump FST (Fast Signal Trace) databases
• gem5
  • Modular simulator platform for computer-system architecture research
• ghdl
  • VHDL 2008/93/87 simulator
• icarus
  • Verilog IEEE-1364 simulator
• ilang
  • Princeton modeling and Verification Platform for SoCs using ILAs
• kaktus2dev
  • Graphical EDA tool based on the IP-XACT standard
• libsystemctlm-soc
  • SystemC/TLM-2.0 Co-simulation framework
• maestro
  • Analytical cost model evaluating DNN mappings (dataflows and tiling)
• opensta
  • Signoff quality STA engine used by OpenRoad
• opentimer
  • High perormance static timing analysis
• osvvm
  • A VHDL verification framework
• qemu
  • Generic and open source machine & userspace emulator and virtualizer
• pono
  • Extensible SMT-based model checker implemented in C++.
• pyucis
  • Python API to Unified Coverage Interoperability Standard (UCIS) Data
• pyuvm
  • SystemVerilog UVM written in Python
• pyvsc
  • Python packages or SystemVerilog UVM style Verification Stimulus and Coverage
• renode
  • Generic and open source machine emulator
• sby
  • Front-end for Yosys-based formal verification flows.
• systemctlm-cosim-demo
  • Demo system for libsystemctlm-soc library
• sv_waveterm
  • Generate text waves in simulation log file
• svlint
  • SystemVerilog linter
• svlint-action
  • GitHub action for svlint
• tce
  • Application-specific instruction-set processor (ASIP) toolset
• uvvm
  • Library for making very structured VHDL-based testbenches.
• verilator
  • SystemVerilog simulator and lint system.
• v2k-top
  • Parser/simulation framework for Verilog & C++
• vidbo
  • Virtual development board
• vunit
  • Unit testing framework for VHDL/SystemVerilog
• z3
  • Microsoft research theorem prover.

Waveform viewers

• d3wave
  • D3.js based wave (signal) visualizer
• gtkwave
  • GTK+ based VCD waveform viewer
• konata
  • Instruction pipeline visualizer for Gem5
• sigrok
  • Portable, signal analysis software suite (logic analyzers, scopes, multimeters, and more)
• simview
  • Text-based SystemVerilog design browser and waveform viewer
• sootty
  • Command-line tool for displaying vcd waveforms

Designs & Generators

Accelerators

• aes
  • Symmetric block cipher AES (Advanced Encryption Standard)
• ara
  • Vector Unit, compatible with the RISC-V Vector Extension
• bfg
  • Compiler for Reduced-Complexity Reconfigurable Fabrics
• BISMO
  • Chisel-based bit-serial matrix multiplication accelerator generator
• FINN
  • Quantized NN to FPGA dataflow accelerator generator
• FFTGenerator
  • MMIO-Based FFT Generator
• fpu
  • Synthesizable ieee 754 floating point library in verilog
• garnet
  • CGRA generator
• gemmini
  • Berkeley Spatial Array Generator
• gplgpu
  • GPL v3 2D/3D graphics engine in verilog
• core_jpeg
  • High throughput JPEG decoder in Verilog for FPGA
• fftgenerator
  • Chisel based FFT generator
• h265-encoder-rtl
  • H.265 Video Encoder IP Core
• LogicNets
  • Train and generate LUT-based neural networks
• NNgen
  • A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
• nvdla
  • NVIDIA Deep Learning Accelerator (NVDLA)
• NyuziProcessor
  • GPGPU microprocessor architecture
• opencgra
  • Parametrizable Coarse-Grained Reconfigurable Array (CGRA) Generator
• openofdm
  • 802.11 OFDM PHY decoder
• openspike
  • Spiking neural network accelerator
• sha3
  • Berkeley SHAR3 ROCC Accelerator
• Serpens
  • HBM FPGA based SpMV Accelerator
• Sextans
  • FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM)
• spiral
  • Spiral based FFT generator
• tvm-vta
  • Opwn, modular, deep learning accelerator
• VeriGOOD-ML
  • Verilog Generator, Optimized for Designs for Machine Learning
• VeriGPU
  • OpenSource GPU, loosely based on RISC-V ISA
• verilog-lfsr
  • Parametrizable combinatorial parallel LFSR/CRC module
• vortex
  • Full-system RISCV-based GPGPU processor

Analog Circuits

• AMS_KGD
  • Repository for Known Good Analog Designs (KGDs)
• analog_blocks
  • Basic building blocks (OTA, BandGap and LDO) in Skywater 130nm.
• openfasoc
  • Fully-Autonomous SoC Synthesis using Customizable Cell-Based Synthesizable Analog Circuits
• open-pmic
  • Current mode buck converter on the SKY130 PDK

Chip Packages

• bsg_packaging
  • Open-Source Hardware Accelerator Packages and Sockets

Boards

• parallella-hw
  • Parallella board design files

Connectivity

• aib
  • Advanced Interface Bus (AIB) die to die hardware
• aib-protocols
  • Advanced Interface Bus (AIB) Protocol IP
• axi
  • AXI SystemVerilog synthesizable IP
• axi4_aib_bridge
  • AXI4/AIB Bridge RTL
• core_ddr3_controller
  • DDR3 memory controller in Verilog for various FPGAs
• hdmi
  • Send video/audio over HDMI on an FPGA
• i2c
  • Fully featured implementation of Inter-IC (I2C) bus master
• litedram
  • Small footprint and configurable DRAM (litex)
• liteeth
  • Small footprint and configurable Ethernet core
• litescope
  • Small footprint and configurable embedded FPGA logic analyzer
• litepice
  • Small footprint and configurable PCIe core
• nocrouter
  • Network-on-Chip Router
• OpenSERDES
  • Digitally synthesizable architecture for SerDes using Skywater130
• pymtl3-net
  • Cornell parameterizable OCN (on-chip network) generator
• ravenoc
  • Configurable HDL NoC (Network-On-Chip)
• tnoc
  • Network on Chip Implementation written in SytemVerilog
• USB3 Camera
  • USB C Industrial Camera Project
• verilog-axis
  • Verilog AXI stream components for FPGA implementation
• verilog-ethernet
  • Verilog Ethernet components for FPGA implementation
• verilog-i2c
  • Verilog I2C interface for FPGA implementation
• verilog-uart
  • Verilog UART
• verilog-pcie
  • Verilog PCI express components
• verilog-wishbone
  • Verilog wishbone components
• wav-d2d-hw
  • 8lane Wlink with D2D and a single AXI Target/Initiator
• wav-lpddr-hw
  • DDR (WDDR) Physical interface (PHY) Hardware
• wav-slink-hw
  • Chiplet link
• wav-wlink-hw
  • Chiplet link

CPUs

• a2i
  • A2I POWER processor core RTL (VHDL)
• black-parrot
  • Linux-capable RISC-V multicore
• cfu-playground
  • Famework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers
• Cores-SweRV
  • SweRV EH1 RISC-Vcore
• Cores-SweRV-EL2
  • SweRV EL2 RISC-V Core
• core-v-verif
  • Functional verification project for the CORE-V family of RISC-V cores
• cva6
  • Linux capable RISC-V CPU
• cv32e40p
  • RV32IMFCX RISC-V 4-stage RISC-V CPU
• ibex
  • Small 32 bit RISC-V CPU core
• microwatt
  • Open POWER ISA softcore written in VHDL 2008
• muntjac
  • Simple 64-bit RISC-V multicore processor
• neorv32
  • Customizable and highly extensible MCU-class 32-bit RISC-V (VHDL)
• OpenXiangShan
  • Open-source high-performance RISC-V processor
• picorv32
  • Size-Optimized RISC-V CPU
• rocket-chip
  • Linux capable RISC-V Rocket Chip Generator
• rioschip
  • Out of order RISC-V core
• serv
  • SErial RISC-V CPU
• snitch
  • Lean but mean RISC-V system
• vroom
  • High performance RISC-V CPU
• warp-v
  • TL-Verilog CPU core/many-core generator (RISC-V, etc.) with visualization

FPGA Architectures

• FABulous
  • Fabric generator and CAD tools
• fabric_team
  • Simple Berkeley FPGA generator class project
• OpenFPGA
  • FPGA IP Generator
• prga
  • Open-source FPGA research and prototyping framework

Libraries

• basejump_stl
  • Library of SystemVerilog components
• basic_verilog
  • Library of SystemVerilog components
• common_cells
  • Library of SystemVerilog components
• hdl
  • Library of Analog Deveices specific components
• oh
  • Library of Verilog components
• pzbcm
  • Basic common modules
• vlsiffra
  • Fast and efficient standard cell based adders, multipliers and multiply-adders

Memory

• core_axi_cache
  • 128KB AXI cache (32-bit in, 256-bit out)
• bsg_fakeram
  • Fake RAM generator
• HuanCun
  • Open-source high-performance non-blocking cache
• openram
  • Static random access memory (SRAM) compiler.
• lake
  • Synthesizable memory generator

Systems

• caliptra
  • Caliptra Root of Trust
• Beagle_SDR_GPS
  • KiwiSDR: BeagleBone web-accessible GPS/SDR
• bsg_manycore
  • Tile based architecture designed for computing efficiency, scalability
• cep
  • RISC-V based Common Evaluation Platform (CEP)
• esp
  • Heterogeneous SoC architecture and IP design platform
• hero
  • FPGA-based research platform for heterogeneous design
• litex
  • SoC builder framework
• openFASOC
  • Open Source FASOC generators
• openpiton
  • General purpose, multithreaded manycore processor
• opentitan
  • Open source silicon root of trust
• openwifi-hw
  • IEEE 802.11 WiFi baseband FPGA (chip) design
• pulp
  • Multicore RISC-V based SoC
• pulpissimo
  • Single core RISC-V based SoC
• SensSeq
  • Mixed-signal system on chip for nanopore-based DNA sequencing
• VerilogBoy
  • Game Boy compatible machine with Verilog

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