DEV-7348: fix 1588TC time error spikes in marvell10g_ptp caused by the PHY's egress drop FIFO

[adrian-nicolau]

Taking inspiration from MTD API, where both mtd_msec_ae_init and mtd_init_macsec disable egress drop FIFO, yet keep ingress drop FIFO active. This setting fixes 1588TC time error spikes observed with Calnex.

The drop buffer supports two operation modes, store-and-forward and cut-through. Mode selection
is accomplished by programming egr_sf_enable, igr_sf_enable field in slc_cfg_gen register.
Each buffer (egress and ingress) can have a separate operation mode. In the store-and-forward
mode, the error packets are completely dropped, while non-error packets passing through the drop
buffer incur a propagation delay proportional to their size.
In the cut-through mode, all packets immediately pass through the drop buffer. Error information is
forwarded to the MAC, and the MAC will transmit error packets with a bad CRC to propagate the
error.

[Copilot]

Pull Request Overview

The PR disables the store-and-forward mode for the egress drop FIFO to eliminate 1588TC time error spikes, implements a helper to clear register bits, and standardizes error logging.

• Introduce MV_V2_SLC_CFG_GEN_EGR_SF_EN bit mask and clear-helper function
• Disable egress SF mode in mv3310_ptp_power_up
• Replace pr_err with dev_err for indirect read errors

Comments suppressed due to low confidence (2)

drivers/net/phy/marvell10g_ptp.c:487

• [nitpick] Add a doxygen-style comment above this function describing its behavior, parameters, and return values, matching the style of mv3310_set_ptp_reg_bits.

static int mv3310_clear_ptp_reg_bits(struct phy_device *phydev,

drivers/net/phy/marvell10g_ptp.c:273

• Consider adding a unit or integration test that verifies the MV_V2_SLC_CFG_GEN_EGR_SF_EN bit is cleared during mv3310_ptp_power_up, ensuring the timing fix is applied and prevent regressions.

/* Disable store-and-forward mode for egress drop FIFO. Without this