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[WIP] device clocks are driven from clockNodes #97

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[WIP] device clocks are driven from clockNodes #97

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73ab2ec
uart: UARTDesignInput has clockNode
hcook Dec 17, 2019
b4f18fb
uart: use ClockGroupIdentityNode
hcook Jan 9, 2020
e60b212
uart: attach via Attachable
hcook Jan 16, 2020
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8 changes: 3 additions & 5 deletions src/main/scala/shell/UARTOverlay.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -5,15 +5,13 @@ import chisel3._
import chisel3.experimental.Analog
import freechips.rocketchip.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem.Attachable
import sifive.blocks.devices.uart._
import freechips.rocketchip.subsystem.{BaseSubsystem, PeripheryBus, PeripheryBusKey}
import freechips.rocketchip.tilelink.TLBusWrapper
import freechips.rocketchip.interrupts.IntInwardNode

//dont make the controller here
//move flowcontrol to shell input??
case class UARTShellInput()
case class UARTDesignInput(uartParams: UARTParams, divInit: Int, controlBus: TLBusWrapper, intNode: IntInwardNode)(implicit val p: Parameters)
case class UARTDesignInput(uartParams: UARTAttachParams, where: Attachable)(implicit val p: Parameters)
case class UARTOverlayOutput(uart: TLUART)
case object UARTOverlayKey extends Field[Seq[DesignPlacer[UARTDesignInput, UARTShellInput, UARTOverlayOutput]]](Nil)
trait UARTShellPlacer[Shell] extends ShellPlacer[UARTDesignInput, UARTShellInput, UARTOverlayOutput]
Expand All @@ -37,7 +35,7 @@ abstract class UARTPlacedOverlay(

def ioFactory = new ShellUARTPortIO(flowControl)

val tluart = UART.attach(UARTAttachParams(di.uartParams, di.divInit, di.controlBus, di.intNode))
val tluart = di.uartParams.attachTo(di.where)
val tluartSink = tluart.ioNode.makeSink
val uartSource = BundleBridgeSource(() => new UARTPortIO())
val uartSink = shell { uartSource.makeSink }
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