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Pull requests: sifive/fpga-shells

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Pull requests list

fix for chipsalliance/rocket-chip#2925
#169 opened May 13, 2022 by sequencer Loading…
remove objectmodule
#168 opened Apr 23, 2022 by sequencer Loading…
fixed parameter of IBUF_DELAY_VALUE type error
#166 opened Oct 25, 2021 by KingFrige Loading…
Add support for Xilinx Virtex UltraScale FPGA VCU108 board
#164 opened Sep 24, 2021 by ariusewy Loading…
fix critical warning for Vivado
#162 opened Apr 25, 2021 by sequencer Loading…
2
add inline blackbox to PowerOnResetFPGAOnly.
#161 opened Apr 19, 2021 by sequencer Loading…
Add support for Xilinx Virtex-7 FPGA VC709 board
#160 opened Mar 25, 2021 by mbs0221 Loading…
Add support for Digilent Genesys 2 board
#159 opened Feb 2, 2021 by yqszxx Loading…
1
SiFive Intel FPGA Direction Request
#131 opened May 18, 2020 by jtarango Loading…
2
[WIP] device clocks are driven from clockNodes
#97 opened Dec 17, 2019 by hcook Loading…
remove api-generator-sifive dependency
#77 opened Jul 19, 2019 by albertchen-sifive Loading…
Add a lot of files for zybo board, so that we can use command line to…
#68 opened Jun 6, 2019 by gongqingfeng Loading…
Adding Future Avalanche Board design files
#57 opened Mar 20, 2019 by CLappin Loading…
Make some of the connector methods more flexible
#41 opened Sep 25, 2018 by mwachs5 Loading…
1
Arty: Allow a slower core clk
#2 opened Sep 6, 2017 by mwachs5 Loading…
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