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bump chipyard to dev + ucb-bar/chipyard#872
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@timsnyder
timsnyder committed Apr 30, 2021
1 parent 029c365 commit 621f46b
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion target-design/chipyard
Submodule chipyard updated 64 files
+5 −5 .circleci/config.yml
+0 −216 .circleci/images/Dockerfile
+0 −18 .circleci/images/README.md
+4 −0 .java_tmp/.gitignore
+61 −0 CHANGELOG.md
+62 −3 build.sbt
+7 −2 common.mk
+67 −0 dockerfiles/Dockerfile
+22 −0 dockerfiles/README.md
+126 −43 docs/Advanced-Concepts/Chip-Communication.rst
+38 −0 docs/Advanced-Concepts/Harness-Clocks.rst
+1 −0 docs/Advanced-Concepts/index.rst
+18 −1 docs/Chipyard-Basics/Initial-Repo-Setup.rst
+26 −3 docs/Customization/Heterogeneous-SoCs.rst
+107 −2 docs/Prototyping/VCU118.rst
+3 −3 docs/TileLink-Diplomacy-Reference/Register-Router.rst
+6 −4 docs/Tools/Barstools.rst
+25 −3 docs/VLSI/Advanced-Usage.rst
+2 −2 docs/VLSI/Tutorial.rst
+ − docs/_static/images/bringup-chipyard-config-communication.png
+ − docs/_static/images/chip-bringup-simulation.png
+ − docs/_static/images/chip-bringup.png
+ − docs/_static/images/chip-communication.png
+ − docs/_static/images/default-chipyard-config-communication.png
+2 −1 docs/requirements.txt
+10 −6 fpga/src/main/resources/vcu118/sdboot/sd.c
+11 −3 fpga/src/main/scala/arty/HarnessBinders.scala
+2 −2 fpga/src/main/scala/arty/TestHarness.scala
+13 −8 fpga/src/main/scala/vcu118/Configs.scala
+14 −8 fpga/src/main/scala/vcu118/TestHarness.scala
+13 −13 fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala
+4 −3 fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
+7 −3 generators/chipyard/src/main/scala/ChipTop.scala
+30 −12 generators/chipyard/src/main/scala/Clocks.scala
+52 −5 generators/chipyard/src/main/scala/ConfigFragments.scala
+2 −0 generators/chipyard/src/main/scala/DigitalTop.scala
+98 −20 generators/chipyard/src/main/scala/HarnessBinders.scala
+21 −3 generators/chipyard/src/main/scala/IOBinders.scala
+74 −7 generators/chipyard/src/main/scala/TestHarness.scala
+2 −5 generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
+4 −1 generators/chipyard/src/main/scala/config/AbstractConfig.scala
+17 −5 generators/chipyard/src/main/scala/config/HeteroConfigs.scala
+29 −0 generators/chipyard/src/main/scala/config/RocketConfigs.scala
+2 −0 generators/chipyard/src/main/scala/config/TracegenConfigs.scala
+1 −1 generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala
+59 −4 generators/firechip/src/main/scala/BridgeBinders.scala
+122 −36 generators/firechip/src/main/scala/FireSim.scala
+34 −33 generators/firechip/src/main/scala/TargetConfigs.scala
+1 −1 generators/gemmini
+1 −1 generators/testchipip
+5 −6 generators/utilities/src/main/scala/Simulator.scala
+27 −10 scripts/build-toolchains.sh
+6 −0 scripts/build-util.sh
+1 −0 scripts/centos-req.sh
+8 −0 scripts/entrypoint.sh
+8 −3 scripts/ubuntu-req.sh
+1 −1 sims/vcs/Makefile
+1 −1 software/firemarshal
+1 −1 software/spec2017
+1 −1 tests/charcount.c
+1 −1 toolchains/esp-tools/riscv-isa-sim
+1 −1 tools/barstools
+2 −1 variables.mk
+4 −0 vlsi/sim.mk

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