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improve RISC-V multi core boot #132

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improve RISC-V multi core boot #132

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Commits on Feb 15, 2024

  1. elfloader/risc-v: clarify parameters and types 

    - Use word_t to adapt to architecture
- sbi_hart_start() takes a custom argument.
- hart ID and custom argument is passed when starting a secondary hart.

Signed-off-by: Axel Heider <axelheider@gmx.de>
    @axel-h
    axel-h committed Feb 15, 2024
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  2. elfloader/risc-v: no need to use t0 

    This also makes the comment about a1 correct again.

Signed-off-by: Axel Heider <axelheider@gmx.de>
    @axel-h
    axel-h committed Feb 15, 2024
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  3. elfloader/risc-v: unify multicore stacks 

    - declare stack fully in C code
- use one array that holds all stack
- use CONFIG_KERNEL_STACK_BITS for size

Signed-off-by: Axel Heider <axelheider@gmx.de>
    @axel-h
    axel-h committed Feb 15, 2024
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  4. elfloader/risc-v: improve comments 

    Signed-off-by: Axel Heider <axelheider@gmx.de>
    @axel-h
    axel-h committed Feb 15, 2024
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  5. elfloader/risc-v: Improve code readability 

    Reorder code blocks and improve comments.

Signed-off-by: Axel Heider <axelheider@gmx.de>
    @axel-h
    axel-h committed Feb 15, 2024
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  6. elfloader/risc-v: add multi core helper functions 

    Use wrapper function to Improve code readability.

Signed-off-by: Axel Heider <axelheider@gmx.de>
    @axel-h
    axel-h committed Feb 15, 2024
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