improve RISC-V multi core boot #405
Workflow file for this run
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| # Copyright 2021, Proofcraft Pty Ltd | |
| # | |
| # SPDX-License-Identifier: BSD-2-Clause | |
| # sel4test simulation runs | |
| # | |
| # See sel4test-sim/builds.yml in the repo seL4/ci-actions for configs. | |
| name: seL4Test | |
| on: | |
| push: | |
| branches: [master] | |
| pull_request: | |
| jobs: | |
| simulation: | |
| name: Simulation | |
| runs-on: ubuntu-latest | |
| strategy: | |
| matrix: | |
| march: [armv7a, armv8a, nehalem, rv32imac, rv64imac] | |
| compiler: [gcc, clang] | |
| steps: | |
| - uses: seL4/ci-actions/sel4test-sim@master | |
| with: | |
| march: ${{ matrix.march }} | |
| compiler: ${{ matrix.compiler }} |