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Commits on Dec 24, 2022

• [SV] Mark SampledOp Pure (llvm#4487)

  uenoku

  authored
  708c632

• [ExportVerilog] Regard dead expressions as inlinable (llvm#4486)

  uenoku

  authored
  89f705b

Commits on Dec 23, 2022

• [LowerSeqToSV] Initialize register element individually (llvm#4478)

  uenoku

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  eb2398b

Commits on Dec 22, 2022

• [LowerToHW] Add extra guards to header macros (llvm#4469)

  uenoku

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  c05bd98

Commits on Dec 20, 2022

• Revert "[LowerToHW] Lower aggregate constant (llvm#4451)" (llvm#4465)

  uenoku

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  b4e042d

• [LowerToHW] Lower aggregate constant (llvm#4451)

  uenoku

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  6c20fa9

Commits on Dec 12, 2022

• Bump llvm (llvm#4432)

  uenoku

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  9bbd2e0

Commits on Dec 8, 2022

• [IMDCE] Improve liveness propagation of input only ports (llvm#4410)

  uenoku

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  17fbc7a

Commits on Dec 2, 2022

• [CombFolds] Fix windows build

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  committed
  d69cb43

• [CombFolds] Handle array operations in flattenConcat (llvm#4389)

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  49c867a

Commits on Dec 1, 2022

• [MergeConnections] Use vector/bundle create and enable aggressive merging by default (llvm#4385)

  uenoku

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  659a409

Commits on Nov 30, 2022

• [FIRRTL][IMCP] Mark aggregate as overdefined (llvm#4370)

  uenoku

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  3363115

Commits on Nov 29, 2022

• [PrepareForEmission] Remove unnecessary tempoary introduced by bitcast op (llvm#4366)

  uenoku

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  6b38c0c

Commits on Nov 24, 2022

• [IMDCE] Generate warnings if empty modules are kept (llvm#4350)

  uenoku

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  1fb05a0

Commits on Nov 17, 2022

• [HWMemSim, LowerSeqToSV] Add a flag to annotate array registers with (*ram_style = "distributed" *) (llvm#4288)

  uenoku

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  e9f443b

Commits on Nov 16, 2022

• Revert "[FIRRTL] Convert Wires To Nodes when dominance allows (llvm#4253)" (llvm#4317)

  uenoku

  authored
  e9e775e

• [LowerToHW] Lower i0 operand in printf-encoded assertions to i1 (llvm#4311)

  uenoku

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  77f14bf

Commits on Nov 15, 2022

• [CI] Swap static and shared library build (llvm#4310)

  uenoku

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  d15bf15

• [LowerToHW] Add a missing null guard

  uenoku

  committed
  9a4568a

• [Seq] Use a new pass generation mechanism (llvm#4304)

  uenoku

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  22d426c

Commits on Nov 10, 2022

• [LowerToHW] Support 1d vector aggregate constant (llvm#4280)

  uenoku

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  29876fb

Commits on Nov 9, 2022

• [SV][Prepare] Improve a namehint propagation and spilling logic (llvm#4261)

  uenoku

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  cf770ec

Commits on Nov 8, 2022

• [LowerToHW] Fix an endiann of vector create (llvm#4260)

  uenoku

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  d00f9ef

• [DropNames] Reuse a droppable name attribute, nfc (llvm#4259)

  uenoku

  authored
  fc0802b

Commits on Nov 4, 2022

• [ExportVerilog] Fix a missed test

  uenoku

  committed
  21905ca

• [ExportVerilog] Legalize keywords by per-basename uniqification (llvm#4221)

  uenoku

  authored
  b96a855

Commits on Nov 1, 2022

• [SV] Implement a canonicalizer to merge neighboring procedural assignments (llvm#4074)

  uenoku

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  e477486

Commits on Oct 31, 2022

• [ExportVerilog] Fix i0 value emission of struct operations (llvm#4208)

  uenoku

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  de1df33

Commits on Oct 27, 2022

• [PruneZeroValuedLogic] Legalize concat/parity/icmp (llvm#4200)

  uenoku

  authored
  fb91326

Commits on Oct 26, 2022

• [LowerToHW, HWMemSimImpl] Remove mux pragmas when size is 1 (llvm#4187)

  uenoku

  authored
  fca36e1

Commits on Oct 24, 2022

• [PrepareForEmission, LoweringOptions] Change spillAllMux to normal option (llvm#4153)

  uenoku

  authored
  c40135e

Commits on Oct 19, 2022

• [Seq] Replace uninitialized aggregate registers with constant zeros (llvm#4120)

  uenoku

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  bf3e923

• [LowerSeqToSV] Apply mux2if transformation to arrays (llvm#4000)

  uenoku

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  5b90e7d

Commits on Oct 14, 2022

• [LowerToHW] Lower subindex into array_get instead of read(array_index) (llvm#4067)

  uenoku

  authored
  0533c02

Commits on Oct 12, 2022

• [ExportVerilog] Remove old emission code (llvm#4079)

  uenoku

  authored
  16d59cc

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