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I am working on a HAL implementation for a UART peripheral and came cross odd behaviour:
...
if status_reader.rdavl().bit_is_set() {
let data = uart.data.read().bits();
Ok((data & 0xff) as u8)
} else {
Err(nb::Error::WouldBlock)
}
...
The rdavl().bit_is_set()
call always returns true
, even when the actual bit in the hardware was not set (I checked in peripheral view and by reading the whole register value as u32
).
I then checked the rdavl()
code in the PAC:
impl R {
#[doc = "Bit 0 - Read Data Available"]
#[inline(always)]
pub fn rdavl(&self) -> RDAVL_R {
RDAVL_R::new(self.bits != 0)
}
#[doc = "Bit 1 - Read Fifo NOT Full"]
#[inline(always)]
pub fn rdnfull(&self) -> RDNFULL_R {
RDNFULL_R::new(((self.bits >> 1) & 0x01) != 0)
}
#[doc = "Bit 2 - RX Busy Receiving"]
#[inline(always)]
pub fn rxbusy(&self) -> RXBUSY_R {
RXBUSY_R::new(((self.bits >> 2) & 0x01) != 0)
}
This is odd. The call does not look correct, it should be RDAVL_R::new((self.bits & 0x01) != 0)
I checked the SVD file:
<name>RXSTATUS</name>
<description>Status Register</description>
<addressOffset>0x010</addressOffset>
<access>read-only</access>
<resetValue>0x0000000</resetValue>
<fields>
<field>
<name>RDAVL</name>
<description>Read Data Available</description>
<bitRange>[0:0]</bitRange>
</field>
<field>
<name>RDNFULL</name>
<description>Read Fifo NOT Full</description>
<bitRange>[1:1]</bitRange>
</field>
Might this be a bug?
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