Check the assembly

.github/workflows/build.yml

@@ -38,7 +38,7 @@ jobs:
           rustup target add ${{ matrix.target }}
       - name: Build
         run: |
-          cargo build --target ${{ matrix.target }} --features "serde, defmt"
+          cargo build --target ${{ matrix.target }} --features "serde, defmt, check-asm"
           cargo build --target ${{ matrix.target }} --no-default-features
 
   build-versatileab:
@@ -126,7 +126,7 @@ jobs:
           rustup component add rust-src --toolchain nightly
       - name: Build
         run: |
-          cargo build --target ${{ matrix.target }} -Zbuild-std=core
+          cargo build --target ${{ matrix.target }} -Zbuild-std=core --features "serde, defmt, check-asm"
           cargo build --target ${{ matrix.target }} -Zbuild-std=core --no-default-features
 
   # Gather all the above build jobs together for the purposes of getting an overall pass-fail

cortex-ar/Cargo.toml

@@ -37,6 +37,7 @@ serde = { version = "1", features = ["derive"], default-features = false, option
 arm-targets = { version = "0.3.0", path = "../arm-targets" }
 
 [features]
+default = []
 # Adds a critical-section implementation that only disables interrupts.
 # This is not sound on multi-core systems because interrupts are per-core.
 critical-section-single-core = ["critical-section"]
@@ -46,6 +47,8 @@ critical-section-multi-core = ["critical-section"]
 # Adds defmt::Format implementation for the register types
 defmt = ["dep:defmt", "arbitrary-int/defmt"]
 serde = ["dep:serde", "arbitrary-int/serde"]
+# Un-inline the asm wrappers so the inline assembly is checked here
+check-asm = []
 
 [package.metadata.docs.rs]
 targets = ["armv7r-none-eabihf", "armv7r-none-eabi", "armv7a-none-eabihf"]

cortex-ar/src/asm.rs

@@ -7,7 +7,7 @@ use core::sync::atomic::{compiler_fence, Ordering};
 /// Ensures that all explicit memory accesses that appear in program order before the `DMB`
 /// instruction are observed before any explicit memory accesses that appear in program order
 /// after the `DMB` instruction.
-#[inline]
+#[cfg_attr(not(feature = "check-asm"), inline)]
 pub fn dmb() {
     compiler_fence(Ordering::SeqCst);
     unsafe {
@@ -23,7 +23,7 @@ pub fn dmb() {
 ///
 ///  * any explicit memory access made before this instruction is complete
 ///  * all cache and branch predictor maintenance operations before this instruction complete
-#[inline]
+#[cfg_attr(not(feature = "check-asm"), inline)]
 pub fn dsb() {
     compiler_fence(Ordering::SeqCst);
     unsafe {
@@ -36,7 +36,7 @@ pub fn dsb() {
 ///
 /// Flushes the pipeline in the processor, so that all instructions following the `ISB` are fetched
 /// from cache or memory, after the instruction has been completed.
-#[inline]
+#[cfg_attr(not(feature = "check-asm"), inline)]
 pub fn isb() {
     compiler_fence(Ordering::SeqCst);
     unsafe {
@@ -46,25 +46,25 @@ pub fn isb() {
 }
 
 /// Emit an NOP instruction
-#[inline]
+#[cfg_attr(not(feature = "check-asm"), inline)]
 pub fn nop() {
     unsafe { core::arch::asm!("nop", options(nomem, nostack, preserves_flags)) }
 }
 
 /// Emit an WFI instruction
-#[inline]
+#[cfg_attr(not(feature = "check-asm"), inline)]
 pub fn wfi() {
     unsafe { core::arch::asm!("wfi", options(nomem, nostack, preserves_flags)) }
 }
 
 /// Emit an WFE instruction
-#[inline]
+#[cfg_attr(not(feature = "check-asm"), inline)]
 pub fn wfe() {
     unsafe { core::arch::asm!("wfe", options(nomem, nostack, preserves_flags)) }
 }
 
 /// Emit an SEV instruction
-#[inline]
+#[cfg_attr(not(feature = "check-asm"), inline)]
 pub fn sev() {
     unsafe {
         core::arch::asm!("sev");
@@ -74,7 +74,7 @@ pub fn sev() {
 /// Which core are we?
 ///
 /// Return the bottom 24-bits of the MPIDR
-#[inline]
+#[cfg_attr(not(feature = "check-asm"), inline)]
 pub fn core_id() -> u32 {
     let r: u32;
     unsafe {

cortex-ar/src/pmsav7.rs

@@ -56,7 +56,7 @@ impl Mpu {
             return None;
         }
         register::Rgnr::write(register::Rgnr(idx as u32));
-        let base = register::Irbar::read().0;
+        let base = register::Irbar::read().0 as *mut u8;
         let rsr = register::Irsr::read();
         let racr = register::Iracr::read();
 
@@ -85,7 +85,7 @@ impl Mpu {
             return None;
         }
         register::Rgnr::write(register::Rgnr(idx as u32));
-        let base = register::Drbar::read().0;
+        let base = register::Drbar::read().0 as *mut u8;
         let rsr = register::Drsr::read();
         let racr = register::Dracr::read();
 
@@ -120,7 +120,7 @@ impl Mpu {
             if !region.size.is_aligned(region.base) {
                 return Err(Error::UnalignedRegion(region.base));
             }
-            register::Irbar::write(register::Irbar(region.base));
+            register::Irbar::write(register::Irbar(region.base as u32));
             register::Irsr::write({
                 let mut out = register::Irsr::new_with_raw_value(0);
                 out.set_enabled(region.enabled);
@@ -145,7 +145,7 @@ impl Mpu {
                 return Err(Error::UnalignedRegion(region.base));
             }
             register::Rgnr::write(register::Rgnr(idx as u32));
-            register::Drbar::write(register::Drbar(region.base));
+            register::Drbar::write(register::Drbar(region.base as u32));
             register::Drsr::write({
                 let mut out = register::Drsr::new_with_raw_value(0);
                 out.set_enabled(region.enabled);

cortex-ar/src/register/actlr.rs

@@ -7,22 +7,27 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Actlr(pub u32);
+
 impl SysReg for Actlr {
     const CP: u32 = 15;
     const CRN: u32 = 1;
     const OP1: u32 = 0;
     const CRM: u32 = 0;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Actlr {}
+
 impl Actlr {
     #[inline]
     /// Reads ACTLR (*Auxiliary Control Register*)
     pub fn read() -> Actlr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Actlr {}
+
 impl Actlr {
     #[inline]
     /// Writes ACTLR (*Auxiliary Control Register*)

cortex-ar/src/register/actlr2.rs

@@ -7,22 +7,27 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Actlr2(pub u32);
+
 impl SysReg for Actlr2 {
     const CP: u32 = 15;
     const CRN: u32 = 1;
     const OP1: u32 = 0;
     const CRM: u32 = 0;
     const OP2: u32 = 3;
 }
+
 impl crate::register::SysRegRead for Actlr2 {}
+
 impl Actlr2 {
     #[inline]
     /// Reads ACTLR2 (*Auxiliary Control Register 2*)
     pub fn read() -> Actlr2 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Actlr2 {}
+
 impl Actlr2 {
     #[inline]
     /// Writes ACTLR2 (*Auxiliary Control Register 2*)

cortex-ar/src/register/adfsr.rs

@@ -7,22 +7,27 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Adfsr(pub u32);
+
 impl SysReg for Adfsr {
     const CP: u32 = 15;
     const CRN: u32 = 5;
     const OP1: u32 = 0;
     const CRM: u32 = 1;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Adfsr {}
+
 impl Adfsr {
     #[inline]
     /// Reads ADFSR (*Auxiliary Data Fault Status Register*)
     pub fn read() -> Adfsr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Adfsr {}
+
 impl Adfsr {
     #[inline]
     /// Writes ADFSR (*Auxiliary Data Fault Status Register*)

cortex-ar/src/register/aidr.rs

@@ -7,14 +7,17 @@ use crate::register::{SysReg, SysRegRead};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Aidr(pub u32);
+
 impl SysReg for Aidr {
     const CP: u32 = 15;
     const CRN: u32 = 0;
     const OP1: u32 = 1;
     const CRM: u32 = 0;
     const OP2: u32 = 7;
 }
+
 impl crate::register::SysRegRead for Aidr {}
+
 impl Aidr {
     #[inline]
     /// Reads AIDR (*Auxiliary ID Register*)

cortex-ar/src/register/aifsr.rs

@@ -7,22 +7,27 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Aifsr(pub u32);
+
 impl SysReg for Aifsr {
     const CP: u32 = 15;
     const CRN: u32 = 5;
     const OP1: u32 = 0;
     const CRM: u32 = 1;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Aifsr {}
+
 impl Aifsr {
     #[inline]
     /// Reads AIFSR (*Auxiliary Instruction Fault Status Register*)
     pub fn read() -> Aifsr {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Aifsr {}
+
 impl Aifsr {
     #[inline]
     /// Writes AIFSR (*Auxiliary Instruction Fault Status Register*)

cortex-ar/src/register/amair0.rs

@@ -7,22 +7,27 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Amair0(pub u32);
+
 impl SysReg for Amair0 {
     const CP: u32 = 15;
     const CRN: u32 = 10;
     const OP1: u32 = 0;
     const CRM: u32 = 3;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for Amair0 {}
+
 impl Amair0 {
     #[inline]
     /// Reads AMAIR0 (*Auxiliary Memory Attribute Indirection Register 0*)
     pub fn read() -> Amair0 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Amair0 {}
+
 impl Amair0 {
     #[inline]
     /// Writes AMAIR0 (*Auxiliary Memory Attribute Indirection Register 0*)

cortex-ar/src/register/amair1.rs

@@ -7,22 +7,27 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Amair1(pub u32);
+
 impl SysReg for Amair1 {
     const CP: u32 = 15;
     const CRN: u32 = 10;
     const OP1: u32 = 0;
     const CRM: u32 = 3;
     const OP2: u32 = 1;
 }
+
 impl crate::register::SysRegRead for Amair1 {}
+
 impl Amair1 {
     #[inline]
     /// Reads AMAIR1 (*Auxiliary Memory Attribute Indirection Register 1*)
     pub fn read() -> Amair1 {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for Amair1 {}
+
 impl Amair1 {
     #[inline]
     /// Writes AMAIR1 (*Auxiliary Memory Attribute Indirection Register 1*)

cortex-ar/src/register/armv8r/cntfrq.rs

@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Cntfrq(pub u32);
+
 impl SysReg for Cntfrq {
     const CP: u32 = 15;
     const CRN: u32 = 14;

cortex-ar/src/register/armv8r/cntp_ctl.rs

@@ -37,6 +37,7 @@ impl SysReg for CntpCtl {
     const CRM: u32 = 2;
     const OP2: u32 = 1;
 }
+
 impl SysRegRead for CntpCtl {}
 
 impl CntpCtl {

cortex-ar/src/register/armv8r/cntp_tval.rs

@@ -7,6 +7,7 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct CntpTval(pub u32);
+
 impl SysReg for CntpTval {
     const CP: u32 = 15;
     const CRN: u32 = 14;

cortex-ar/src/register/armv8r/cntv_tval.rs

@@ -7,22 +7,27 @@ use crate::register::{SysReg, SysRegRead, SysRegWrite};
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct CntvTval(pub u32);
+
 impl SysReg for CntvTval {
     const CP: u32 = 15;
     const CRN: u32 = 14;
     const OP1: u32 = 0;
     const CRM: u32 = 3;
     const OP2: u32 = 0;
 }
+
 impl crate::register::SysRegRead for CntvTval {}
+
 impl CntvTval {
     #[inline]
     /// Reads CNTV_TVAL (*Virtual Counter-timer TimerValue Register*)
     pub fn read() -> CntvTval {
         unsafe { Self(<Self as SysRegRead>::read_raw()) }
     }
 }
+
 impl crate::register::SysRegWrite for CntvTval {}
+
 impl CntvTval {
     #[inline]
     /// Writes CNTV_TVAL (*Virtual Counter-timer TimerValue Register*)