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jonathanpallant merged 1 commit into from
Jul 6, 2026
Merged

Clean up handler comments #201

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60 changes: 30 additions & 30 deletions aarch32-rt/src/arch_v4/abort.rs
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Expand Up @@ -13,28 +13,28 @@ core::arch::global_asm!(
.global _asm_default_data_abort_handler
.type _asm_default_data_abort_handler, %function
_asm_default_data_abort_handler:
sub lr, lr, #8 // Subtract 8 from LR, see p.1214 of the ARMv7-A architecture manual.
push {{ r12 }} // Save preserved register R12 - can now use it
mrs r12, spsr // grab SPSR
push {{ r12 }} // save SPSR value
and r12, sp, 7 // align SP down to eight byte boundary using R12
sub sp, r12 // SP now aligned - only push 64-bit values from here
push {{ r0-r4, r12 }} // push alignment amount, and preserved registers - can now use R0-R3 (R4 is just padding)
sub lr, lr, #8 // Make sure we jump back to the right place
push {{ r12 }} // Push preserved register R12 (1)
mrs r12, spsr // Grab SPSR (2)
push {{ r12 }} // Push SPSR value (3)
and r12, sp, 7 // Align SP down to eight byte boundary using R12
sub sp, r12 // SP now aligned - only push 64-bit values from here (4)
push {{ r0-r4, r12 }} // Push preserved registers and alignment amount (R4 is just padding) (5)
"#,
crate::fpu_context!("save"),
r#"
mov r0, lr // Pass the faulting instruction address to the handler.
bl _data_abort_handler // call C handler
mov lr, r0 // if we get back here, assume they returned a new LR in r0
bl _data_abort_handler // Call C handler
mov lr, r0 // If we get back here, assume they returned a new LR in r0
"#,
crate::fpu_context!("restore"),
r#"
pop {{ r0-r4, r12 }} // restore preserved registers, dummy value, and alignment amount
add sp, r12 // restore SP alignment using R12
pop {{ r12 }} // restore SPSR using R12
msr spsr, r12 //
pop {{ r12 }} // restore R12
movs pc, lr // return from exception
pop {{ r0-r4, r12 }} // Pop preserved registers, dummy value, and alignment amount to undo (5)
add sp, r12 // Restore SP alignment using R12 to undo (4)
pop {{ r12 }} // Pop saved SPSR value to undo (3)
msr spsr, r12 // Restore SPSR using R12 to undo (2)
pop {{ r12 }} // Pop R12 to undo (1)
movs pc, lr // Return from exception
.size _asm_default_data_abort_handler, . - _asm_default_data_abort_handler
.popsection
"#
Expand All @@ -53,28 +53,28 @@ core::arch::global_asm!(
.global _asm_default_prefetch_abort_handler
.type _asm_default_prefetch_abort_handler, %function
_asm_default_prefetch_abort_handler:
sub lr, lr, #4 // Subtract 4 from LR, see p.1212 of the ARMv7-A architecture manual.
push {{ r12 }} // Save preserved register R12 - can now use it
mrs r12, spsr // grab SPSR
push {{ r12 }} // save SPSR value
and r12, sp, 7 // align SP down to eight byte boundary using R12
sub sp, r12 // SP now aligned - only push 64-bit values from here
push {{ r0-r4, r12 }} // push alignment amount, and preserved registers - can now use R0-R3 (R4 is just padding)
sub lr, lr, #4 // Make sure we jump back to the right place
push {{ r12 }} // Push preserved register R12 (1)
mrs r12, spsr // Grab SPSR (2)
push {{ r12 }} // Push SPSR value (3)
and r12, sp, 7 // Align SP down to eight byte boundary using R12
sub sp, r12 // SP now aligned - only push 64-bit values from here (4)
push {{ r0-r4, r12 }} // Push preserved registers and alignment amount (R4 is just padding) (5)
"#,
crate::fpu_context!("save"),
r#"
mov r0, lr // Pass the faulting instruction address to the handler.
bl _prefetch_abort_handler // call C handler
mov lr, r0 // if we get back here, assume they returned a new LR in r0
bl _prefetch_abort_handler // Call C handler
mov lr, r0 // If we get back here, assume they returned a new LR in r0
"#,
crate::fpu_context!("restore"),
r#"
pop {{ r0-r4, r12 }} // restore preserved registers, dummy value, and alignment amount
add sp, r12 // restore SP alignment using R12
pop {{ r12 }} // restore SPSR using R12
msr spsr, r12 //
pop {{ r12 }} // restore R12
movs pc, lr // return from exception
pop {{ r0-r4, r12 }} // Pop preserved registers, dummy value, and alignment amount to undo (5)
add sp, r12 // Restore SP alignment using R12 to undo (4)
pop {{ r12 }} // Grab saved SPSR to undo (3)
msr spsr, r12 // Restore SPSR using R12 to undo (2)
pop {{ r12 }} // Pop R12 to undo (1)
movs pc, lr // Return from exception
.size _asm_default_prefetch_abort_handler, . - _asm_default_prefetch_abort_handler
.popsection
"#,
Expand Down
32 changes: 16 additions & 16 deletions aarch32-rt/src/arch_v4/interrupt.rs
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Expand Up @@ -30,29 +30,29 @@ core::arch::global_asm!(
.global _asm_default_irq_handler
.type _asm_default_irq_handler, %function
_asm_default_irq_handler:
sub lr, lr, 4 // make sure we jump back to the right place
stmfd sp!, {{ lr }} // save adjusted LR to IRQ stack (1)
mrs lr, spsr // The hardware has copied the interrupted task's CPSR to SPSR_irq - grab it (2) and
push {{ lr }} // save it to IRQ stack using LR (3)
msr cpsr_c, {handler_mode} // switch to handler mode (4)
push {{ lr }} // Save LR of handler mode before using it for stack alignment (5)
and lr, sp, 7 // align SP down to eight byte boundary using LR
sub lr, lr, 4 // Make sure we jump back to the right place
stmfd sp!, {{ lr }} // Save adjusted LR to IRQ stack (1)
mrs lr, spsr // Grab SPSR (2)
push {{ lr }} // Push SPSR value (3)
msr cpsr_c, {handler_mode} // Switch to handler mode (4)
push {{ lr }} // Push LR of handler mode before using it for stack alignment (5)
and lr, sp, 7 // Align SP down to eight byte boundary using LR
sub sp, lr // SP now aligned - only push 64-bit values from here (6)
push {{ r0-r3, r12, lr }} // push alignment amount (in LR) and preserved registers (7)
push {{ r0-r3, r12, lr }} // Push preserved registers and alignment amount (7)
"#,
crate::fpu_context!("save"),
r#"
bl _irq_handler // call C handler in the selected handler mode (they may choose to re-enable interrupts)
bl _irq_handler // Call C handler in the selected handler mode (they may choose to re-enable interrupts)
"#,
crate::fpu_context!("restore"),
r#"
pop {{ r0-r3, r12, lr }} // restore alignment amount (in LR) and preserved registers to undo (7)
add sp, lr // restore SP alignment using LR to undo (6)
pop {{ lr }} // Restore the actual link register of handler mode to undo (5)
msr cpsr_c, {irq_mode} // switch back to IRQ mode (with IRQ masked) to undo (4)
pop {{ lr }} // load SPSR to undo (3)
msr spsr, lr // restore SPSR to undo (2)
ldmfd sp!, {{ pc }}^ // return from exception (^ => restore SPSR to CPSR) to undo (1)
pop {{ r0-r3, r12, lr }} // Pop alignment amount (in LR) and preserved registers to undo (7)
add sp, lr // Restore SP alignment using LR to undo (6)
pop {{ lr }} // Pop the actual link register of handler mode to undo (5)
msr cpsr_c, {irq_mode} // Switch back to IRQ mode (with IRQ masked) to undo (4)
pop {{ lr }} // Grab saved SPSR to undo (3)
msr spsr, lr // Restore SPSR using LR to undo (2)
ldmfd sp!, {{ pc }}^ // Return from exception to undo (1) (^ => restore SPSR to CPSR)
.size _asm_default_irq_handler, . - _asm_default_irq_handler
.popsection
"#,
Expand Down
32 changes: 16 additions & 16 deletions aarch32-rt/src/arch_v4/svc.rs
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Expand Up @@ -14,13 +14,13 @@ core::arch::global_asm!(
.global _asm_default_svc_handler
.type _asm_default_svc_handler, %function
_asm_default_svc_handler:
push {{ r12, lr }} // save LR and R12 - can now use R12 (but leave LR alone for SVC code lookup)
mrs r12, spsr // grab SPSR using R12
push {{ r12 }} // save SPSR value
and r12, sp, 7 // align SP down to eight byte boundary using R12
sub sp, r12 // SP now aligned - only push 64-bit values from here
push {{ r0-r6, r12 }} // push alignment amount, and stacked SVC argument registers (must be even number of regs for alignment)
mov r12, sp // save SP for integer frame
stmfd sp!, {{ r12, lr }} // Save LR and R12 (1)
mrs r12, spsr // Grab SPSR (2)
push {{ r12 }} // Push SPSR value (3)
and r12, sp, 7 // Align SP down to eight byte boundary using R12
sub sp, r12 // SP now aligned - only push 64-bit values from here (4)
push {{ r0-r6, r12 }} // Push SVC frame registers and alignment amount (5)
mov r12, sp // Save SP for integer frame
"#,
crate::fpu_context!("save"),
r#"
Expand All @@ -33,18 +33,18 @@ core::arch::global_asm!(
ldr r0, [lr,#-4] // No: Load word and...
bic r0, r0, #0xFF000000 // ...extract 3-byte immediate
2:
mov r1, r12 // pass the stacked integer registers in r1
bl _svc_handler
mov lr, r0 // move r0 out of the way - restore_fpu_context will trash it
mov r1, r12 // Pass the stacked integer registers in r1
bl _svc_handler // Call C handler in SVC mode
mov lr, r0 // Move r0 out of the way - restore_fpu_context will trash it
"#,
crate::fpu_context!("restore"),
r#"
pop {{ r0-r6, r12 }} // restore stacked registers and alignment amount
mov r0, lr // replace R0 with return value from _svc_handler
add sp, r12 // restore SP alignment using R12
pop {{ lr }} // restore SPSR using LR
msr spsr, lr //
ldmfd sp!, {{ r12, pc }}^ // restore R12 and return from exception (^ => restore SPSR to CPSR)
pop {{ r0-r6, r12 }} // Pop SVC frame registers and alignment amount to undo (5)
mov r0, lr // Replace R0 with return value from _svc_handler
add sp, r12 // Restore SP alignment using R12 to undo (4)
pop {{ r12 }} // Grab saved SPSR to undo (3)
msr spsr, r12 // Restore SPSR using R12 to undo (2)
ldmfd sp!, {{ r12, pc }}^ // Restore R12 and return from exception (^ => restore SPSR to CPSR) to undo (1)
.size _asm_default_svc_handler, . - _asm_default_svc_handler
.popsection
"#,
Expand Down
28 changes: 14 additions & 14 deletions aarch32-rt/src/arch_v4/undefined.rs
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Expand Up @@ -16,31 +16,31 @@ core::arch::global_asm!(
.global _asm_default_undefined_handler
.type _asm_default_undefined_handler, %function
_asm_default_undefined_handler:
push {{ r12 }} // save R12 - can now use it
mrs r12, spsr // grab SPSR using R12
push {{ r12 }} // save SPSR value
push {{ r12 }} // Push preserved register R12 (1)
mrs r12, spsr // Grab SPSR (2)
push {{ r12 }} // Push SPSR value (3)
tst r12, {t_bit} // Was the code that triggered the exception in Thumb state?
ite eq // Adjust LR to point to faulting instruction - see p.1206 of the ARMv7-A architecture manual.
subeq lr, lr, #4 // Subtract 4 in Arm Mode
subne lr, lr, #2 // Subtract 2 in Thumb Mode
and r12, sp, 7 // align SP down to eight byte boundary using R12
sub sp, r12 // SP now aligned - only push 64-bit values from here
push {{ r0-r4, r12 }} // push alignment amount, and preserved registers - can now use R0-R3 (R4 is just padding)
and r12, sp, 7 // Align SP down to eight byte boundary using R12
sub sp, r12 // SP now aligned - only push 64-bit values from here (4)
push {{ r0-r4, r12 }} // Push alignment amount, and preserved registers (R4 is just padding) (5)
"#,
crate::fpu_context!("save"),
r#"
mov r0, lr // Pass the faulting instruction address to the handler.
bl _undefined_handler // call C handler
mov lr, r0 // if we get back here, assume they returned a new LR in r0
bl _undefined_handler // Call C handler
mov lr, r0 // If we get back here, assume they returned a new LR in r0
"#,
crate::fpu_context!("restore"),
r#"
pop {{ r0-r4, r12 }} // restore preserved registers, dummy value, and alignment amount
add sp, r12 // restore SP alignment using R12
pop {{ r12 }} // restore SPSR using R12
msr spsr, r12 //
pop {{ r12 }} // restore R12
movs pc, lr // return from exception (movs => restore SPSR to CPSR)
pop {{ r0-r4, r12 }} // Pop preserved registers, dummy value, and alignment amount to undo (5)
add sp, r12 // Restore SP alignment using R12 to undo (4)
pop {{ r12 }} // Grab saved SPSR to undo (3)
msr spsr, r12 // Restore SPSR using LR to undo (2)
pop {{ r12 }} // Pop R12 to undo (1)
movs pc, lr // Return from exception (movs => restore SPSR to CPSR)
.size _asm_default_undefined_handler, . - _asm_default_undefined_handler
.popsection
"#,
Expand Down
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