Releases: riscv/riscv-debug-spec
1.0.0-rc3
What's Changed
- dmactive is part of dmcontrol, and debug module version is from dmstatus by @stefano-codasip in #1003
- Remove an extra 'already' in [5.7. Trigger Module Registers] by @en-sc in #1010
- fix a reference to
mcontrol.store
field by @en-sc in #1012 - "Native Triggers": Add in mepc/mcause back in. by @rtwfroody in #1020
- Restore references to
mhartid
indebug_module.adoc
by @en-sc in #1022 - Add support for Smdbltrp. by @rtwfroody in #998
- 1.0.0-rc2 by @rtwfroody in #988
- Don't trademark the trigger module by @gameboo in #1027
- Restore references to
command.cmdtype
andtab:cmdtype
table by @en-sc in #1030 - Restore reference to
dmstatus.impebreak
by @en-sc in #1031 - Fix a typo in [3.12. Security] by @en-sc in #1032
- Restore references to
pc
in [3.8. Program Buffer] by @en-sc in #1033 - [3.14.6. Abstract Control and Status] make
busy
a reference by @en-sc in #1034 - Fix formatting for
mconfigptr
by @en-sc in #1035 - Fix references to
sbcs.sbaccess64/128
by @en-sc in #1036 - Restore reference to
time
by @en-sc in #1037 - Replace single quotes with backticks in
mstatus
reference by @en-sc in #1038 - Replace "count" with a reference to 'icount.count' by @en-sc in #1039
- Eliminate redundant statement about AMO's stored value availability by @en-sc in #1024
- Clarify timing support suggestion for a chain of mcontrol load triggers by @en-sc in #1023
- Simplify WARL description for dmode=0 and action=1. by @rtwfroody in #1009
New Contributors
Full Changelog: 1.0.0-rc2.1...1.0.0-rc3
1.0.0-rc2.1, rc2 plus typo/formatting fixes
This release fixes typos (mostly related to internal document links) and formatting compared to the previous 1.0.0-rc2 release.
The changes that are not merely typo/formatting changes are listed at #988
smdbltrp
This includes all changes required to add Smdbltrp support to the Debug Spec.
These changes only affect the dcsr register. You can see the exact changes at https://github.com/riscv/riscv-debug-spec/pull/998/files
1.0.0-rc2
This is sent over to ARC as a final set of changes before ratification.
Pull Request that contains all these changes together: #988
Significant Changes
- Remove Section 4.9: XLEN by @rtwfroody in #984
- Clarify textra behavior when XLEN changes. by @rtwfroody in #978
- Fix contradictory req. for ndmresetpending by @JanMatCodasip in #951
- Make the data of the *context registers 32 bits wide. by @rtwfroody in #981
- Load data before trigger priority was ambiguous. by @rtwfroody in #987
1.0.0-rc1 asciidoc
Merge pull request #971 from riscv/merge_asciidoc Convert to asciidoc
Freeze Candidate
Identical to AR 2023-12-08. See https://github.com/riscv/riscv-debug-spec/releases/tag/ar20231208 for details about changes added during the AR process.
AR 2023-12-08
Note: There's a PDF link at the bottom of this page.
Full Changelog since AR 2023-09-11: ar20230911...ar20231208
Full Changelog since AR 2023-09-14: ar20230914...ar20231208
Full Changelog since AR 2023-10-04: ar20231004...ar20231208
Full Changelog since AR 2023-10-12: ar20231012...ar20231208
What's Changed since AR 2023-10-12
- AR: Comment etrigger limited to 32 exceptions if XLEN=32 by @timsifive in #907
- AR: Comment itrigger limited to 32 ints if XLEN=32 by @timsifive in #906
- non-spec: Fix macro generation by @kr-sc in #902
- non-spec: The last field of a register was not printed by @en-sc in #908
- non-spec: Make register dump output more concise. by @timsifive in #909
- uncertain is updated when trigger fires. by @timsifive in #916
- Refer to "trigger registers" as "Trigger Module Registers" by @timsifive in #917
- Trigger CSRs provide access to underlying triggers. by @timsifive in #918
- CSR reset values apply to underlying triggers. by @timsifive in #920
- non-spec: Remove unnecessary parens. by @timsifive in #922
- Invalid addresses might not match. by @timsifive in #911
What's Changed since AR 2023-10-04
- AR: Update priority table from latest privspec by @timsifive in #897
- Add people with git PRs to credits. by @timsifive in #900
- AR: Clarify itrigger behavior. by @timsifive in #901
- AR: Clarify itrigger and trigger number translation by @timsifive in #903
Full Changelog: ar20231004...ar20231012
What's Changed since AR 2023-09-14
- Address review comments on
debug_defines.h
by @en-sc in #876 - Fix debugger examples: use transfer with write by @timsifive in #886
- AR: List which extensions were considered. by @timsifive in #881
- dscratch[01] are DXLEN bits wide. by @timsifive in #885
- AR: Clarify unimplemented Sdtrig. by @timsifive in #879
- AR: Clarify mcontext/hcontext. by @timsifive in #882
- AR: Remove Message Registers. by @timsifive in #878
- AR: tcontrol.mie applies to all traps, not just breakpoints by @timsifive in #880
- Clean up Makefile a little by @timsifive in #887
- AR: Clarify section/chapter in Sdext. by @timsifive in #895
- AR: Clarify why icount matches on every trap. by @timsifive in #896
- AR: Clarify what tmexttrigger.intctl is for by @timsifive in #898
- AR: Define mcontrol* triggers and multiple accesses by @timsifive in #883
- AR: Clarify triggers and multiple state changes by @timsifive in #899
What's Changed since AR 2023-09-11
- AR: Remove comment about privspec/CSR behavior by @timsifive in #874
- AR: Clarify what debuggers can assume about MRs by @timsifive in #875
AR 2023-10-12
This has merged changes in response to every piece of AR feedback we have received.
What's Changed since AR 2023-10-04
- AR: Update priority table from latest privspec by @timsifive in #897
- Add people with git PRs to credits. by @timsifive in #900
- AR: Clarify itrigger behavior. by @timsifive in #901
- AR: Clarify itrigger and trigger number translation by @timsifive in #903
Full Changelog: ar20231004...ar20231012
What's Changed since AR 2023-09-14
- Address review comments on
debug_defines.h
by @en-sc in #876 - Fix debugger examples: use transfer with write by @timsifive in #886
- AR: List which extensions were considered. by @timsifive in #881
- dscratch[01] are DXLEN bits wide. by @timsifive in #885
- AR: Clarify unimplemented Sdtrig. by @timsifive in #879
- AR: Clarify mcontext/hcontext. by @timsifive in #882
- AR: Remove Message Registers. by @timsifive in #878
- AR: tcontrol.mie applies to all traps, not just breakpoints by @timsifive in #880
- Clean up Makefile a little by @timsifive in #887
- AR: Clarify section/chapter in Sdext. by @timsifive in #895
- AR: Clarify why icount matches on every trap. by @timsifive in #896
- AR: Clarify what tmexttrigger.intctl is for by @timsifive in #898
- AR: Define mcontrol* triggers and multiple accesses by @timsifive in #883
- AR: Clarify triggers and multiple state changes by @timsifive in #899
Full Changelog: ar20230914...ar20231012
AR 2023-10-04
Another version for Architecture Review. Does not yet address all the Sdtrig feedback.
What's Changed
- Address review comments on
debug_defines.h
by @en-sc in #876 - Fix debugger examples: use transfer with write by @timsifive in #886
- AR: List which extensions were considered. by @timsifive in #881
- dscratch[01] are DXLEN bits wide. by @timsifive in #885
- AR: Clarify unimplemented Sdtrig. by @timsifive in #879
- AR: Clarify mcontext/hcontext. by @timsifive in #882
- AR: Remove Message Registers. by @timsifive in #878
- AR: tcontrol.mie applies to all traps, not just breakpoints by @timsifive in #880
- Clean up Makefile a little by @timsifive in #887
- AR: Clarify section/chapter in Sdext. by @timsifive in #895
- AR: Clarify why icount matches on every trap. by @timsifive in #896
- AR: Clarify what tmexttrigger.intctl is for by @timsifive in #898
- AR: Define mcontrol* triggers and multiple accesses by @timsifive in #883
- AR: Clarify triggers and multiple state changes by @timsifive in #899
Full Changelog: ar20230914...ar20231004