Strengthen atomic_compare_exchange seq_cst failure mapping #445
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Happy to update formatting/verbage. An alternative format would to |
aswaterman
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Jul 15, 2024
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Thanks for the review! |
The Zacas extension defines different ordering behavior when an amocas fails: > The memory operation performed by an AMOCAS.W/D/Q, when not successful, has > acquire semantics if aq bit is 1 but does not have release semantics, > regardless of rl. This requires a leading fence to maintain A6C compatability for both the RVWMO and Ztso memory models. The A7 mappings can use the non-fenced versions. See issue riscv-non-isa#444 for more context and litmus tests. Resolves riscv-non-isa#444.
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Updated to address @hboehm's review by adding note-3 to the Ztso table. |
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The discussion has concluded so I think this is OK to land. |
kito-cheng
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Jul 23, 2024
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… to ABI change The psABI was updated to note that a leading fence must be present for amocas with seq_cst failure ordering. <riscv-non-isa/riscv-elf-psabi-doc#445>. shouldInsertFencesForAtomic only returns true for AtomicCmpXchg if Zacas is present, because doing so otherwise changes codegen due to how the atomic expansion pass handles this hook.
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…hange A recent atomics ABI change / fix requiresthat for the "A6C" and A6S" atomics ABIs (i.e. both of those supported by LLVM currently), an additional fence is inserted for an atomic_compare_exchange with seq_cst failure ordering. <riscv-non-isa/riscv-elf-psabi-doc#445> This isn't trivial to support through the hooks used by AtomicExpandPass because that pass assumes that when fences are inserted, the original atomics ordering information can be removed from the instruction. Rather than try to change and complicate that API, this patch implements the needed fence insertion in RISCVCodeGenPrepare.
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…hange A recent atomics ABI change / fix requiresthat for the "A6C" and A6S" atomics ABIs (i.e. both of those supported by LLVM currently), an additional fence is inserted for an atomic_compare_exchange with seq_cst failure ordering. <riscv-non-isa/riscv-elf-psabi-doc#445> This isn't trivial to support through the hooks used by AtomicExpandPass because that pass assumes that when fences are inserted, the original atomics ordering information can be removed from the instruction. Rather than try to change and complicate that API, this patch implements the needed fence insertion in RISCVCodeGenPrepare.
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…hange (#101023) A recent atomics ABI change / fix requires that for the "A6C" and A6S" atomics ABIs (i.e. both of those supported by LLVM currently), an additional fence is inserted for an atomic_compare_exchange with seq_cst failure ordering. <riscv-non-isa/riscv-elf-psabi-doc#445> This isn't trivial to support through the hooks used by AtomicExpandPass because that pass assumes that when fences are inserted, the original atomics ordering information can be removed from the instruction. Rather than try to change and complicate that API, this patch implements the needed fence insertion through a small special purpose pass.
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…hange (llvm#101023) A recent atomics ABI change / fix requires that for the "A6C" and A6S" atomics ABIs (i.e. both of those supported by LLVM currently), an additional fence is inserted for an atomic_compare_exchange with seq_cst failure ordering. <riscv-non-isa/riscv-elf-psabi-doc#445> This isn't trivial to support through the hooks used by AtomicExpandPass because that pass assumes that when fences are inserted, the original atomics ordering information can be removed from the instruction. Rather than try to change and complicate that API, this patch implements the needed fence insertion through a small special purpose pass.
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The Zacas extension defines different ordering behavior when an amocas fails:
This requires a leading fence to maintain A6C compatability for both the RVWMO and Ztso memory models. The A7 mappings can use the non-fenced versions.
See issue #444 for more context and litmus tests.
Resolves #444.