Skip to content
@riscv-non-isa

RISC-V Non-ISA Specifications

The Open-Standard Instruction Set Architecture
README.md

Welcome to the RISC-V Non-ISA Specifications 👋

RISC-V Logo

Non-ISA specifications do not add new instructions, create or change opcodes, or in any way modify the RISC-V ISA. They do help us to develop an ecosystem around the ISA Specifications.

Things you'll find here include:

  • ABI Documentation
  • Architecture Tests
  • Specifications like Debug, Processor Trace, and Software Interrupts

If you don't find what you're looking for here, try one of our other GitHub organizations:

Popular repositories Loading

  1. riscv-asm-manual riscv-asm-manual Public

    RISC-V Assembly Programmer's Manual

    Makefile 1.6k 250

  2. riscv-elf-psabi-doc riscv-elf-psabi-doc Public

    A RISC-V ELF psABI Document

    Python 817 179

  3. riscv-arch-test riscv-arch-test Public

    Assembly 614 252

  4. riscv-sbi-doc riscv-sbi-doc Public

    Documentation for the RISC-V Supervisor Binary Interface

    Makefile 445 99

  5. rvv-intrinsic-doc rvv-intrinsic-doc Public

    C 351 105

  6. riscv-trace-spec riscv-trace-spec Public

    RISC-V Processor Trace Specification

    C 198 57

Repositories

Showing 10 of 35 repositories
  • riscv-iommu Public

    RISC-V IOMMU Specification

    riscv-non-isa/riscv-iommu’s past year of commit activity
    C 144 CC-BY-4.0 29 2 3 Updated Dec 6, 2025
  • riscv-arch-test Public
    riscv-non-isa/riscv-arch-test’s past year of commit activity
    Assembly 614 Apache-2.0 252 60 60 Updated Dec 5, 2025
  • riscv-event-trace Public

    Extension to the RISC-V Trace standards which is user-configurable to trace a hardware-filtered subset of instructions

    riscv-non-isa/riscv-event-trace’s past year of commit activity
    Makefile 0 CC-BY-4.0 0 0 1 Updated Dec 5, 2025
  • iopmp-spec Public

    This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.

    riscv-non-isa/iopmp-spec’s past year of commit activity
    C 37 CC-BY-4.0 9 2 1 Updated Dec 5, 2025
  • riscv-security-model Public

    RISC-V Security Model

    riscv-non-isa/riscv-security-model’s past year of commit activity
    Makefile 33 CC-BY-4.0 17 2 1 Updated Dec 5, 2025
  • riscv-semihosting Public
    riscv-non-isa/riscv-semihosting’s past year of commit activity
    Makefile 32 CC-BY-SA-4.0 11 2 2 Updated Dec 5, 2025
  • riscv-acpi-rimt Public

    RISC-V ACPI I/O Mapping Table Specification

    riscv-non-isa/riscv-acpi-rimt’s past year of commit activity
    Makefile 7 CC-BY-4.0 4 2 1 Updated Dec 5, 2025
  • riscv-c-api-doc Public

    Documentation of the RISC-V C API

    riscv-non-isa/riscv-c-api-doc’s past year of commit activity
    Makefile 77 CC-BY-4.0 47 15 5 Updated Dec 5, 2025
  • riscv-brs Public

    The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectations for the Operating System (OS) to utilize in acts of device discovery, system management, and other rich operations provided in this specification.

    riscv-non-isa/riscv-brs’s past year of commit activity
    TeX 55 CC-BY-4.0 20 15 1 Updated Dec 5, 2025
  • riscv-external-debug-security Public

    The RISC-V External Debug Security Specification

    riscv-non-isa/riscv-external-debug-security’s past year of commit activity
    Makefile 20 CC-BY-4.0 4 0 2 Updated Dec 5, 2025
View all repositories

People

This organization has no public members. You must be a member to see who’s a part of this organization.