Implement Relaxations from RISC-V ELF psABI Qualcomm Extensions

[lenary]

The release at https://github.com/quic/riscv-elf-psabi-quic-extensions/releases/tag/v0.2 describes several relaxations for the Xqci instructions/relocations, which we want to implement in eld.

The intention is to implement them behind a --relax-xqci flag, so that standard implementations are not affected. This will work like --no-relax-c, but be disabled-by-default.

The relaxations we intend to implement, in order and grouped together, are:

• "Extended to Standard Function/Tail Call" and "Extended to Compressed Function/Tail Call"
  (QC.E.JAL -> C.JAL or JAL ra; QC.E.J -> C.J or JAL x0) ([RISCV] Implement Relaxations for QC.E.J/QC.E.JAL #140)
• "Extended to Standard Address", "Extended to Compressed LUI Relaxation", and "Extended to Standard Global-pointer Address Relaxation"
  (QC.E.LI -> C.LUI, QC.LI, or ADDI (gp-relative); QC.LI -> C.LUI) ([RISCV] Implement Relaxations for QC.E.LI/QC.LI #194)
• "Standard to Extended Function/Tail Call Relaxation"
  (AUIPC; JALR ra -> QC.E.JAL; AUIPC; JALR x0 -> QC.E.J) ([RISCV] Implement Xqci Call Relaxations #201)
• "Standard to Extended address relaxation", "Standard to Extended global-pointer address relaxation", and "Zero-page address relaxation"
  (LUI; ADDI -> QC.LI, QC.E.LI, or QC.E.ADDI (gp-relative))
• "Standard to Extended Zero-page Load/Store Relaxation" and "Standard to Extended Global-pointer relaxation"
  (LUI; L{W,H,HU,B,BU} -> QC.E.L{W,H,HU,B,BU} (zero- or gp-relative); LUI; S{W,H,B} -> QC.E.S{W,H,B})

For the two-instruction sequences starting LUI, we will likely also end up relaxing the AUIPC equivalent, but this depends on being able to tell whether the user wants the resulting image to be position-independent or not.

[lenary]

I believe this is now complete. We released a new version of the spec removing the relaxations of hi/lo paired relocations: https://github.com/quic/riscv-elf-psabi-quic-extensions/releases/tag/v0.3

I will file a new issue if we find future work.